4.3.21. Cache Size ID Register

The CCSIDR characteristics are:

Purpose

Provides information about the architecture of the caches.

Usage constraints

The CCSIDR is:

  • a read-only register

  • Common to the Secure and Non-secure states

  • only accessible from PL1 or higher.

Configurations

There is one CCSIDR for each cache that it can access. The CSSELR selects which Cache Size ID Register is accessible.

Attributes

See the register summary in Table 4.2.

Figure 4.18 shows the CCSIDR bit assignments.

Figure 4.18. CCSIDR bit assignments

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Table 4.46 shows the CCSIDR bit assignments.

Table 4.46. CCSIDR bit assignments

BitsNameFunction
[31]WT

Indicates support for Write-Through:

0

Cache level does not support Write-Through.

1

Cache level supports Write-Through.

[30]WB

Indicates support for Write-Back:

0

Cache level does not support Write-Back.

1

Cache level supports Write-Back.

[29]RA

Indicates support for Read-Allocation:

0

Cache level does not support Read-Allocation.

1

Cache level supports Read-Allocation.

[28]WA

Indicates support for Write-Allocation:

0

Cache level does not support Write-Allocation.

1

Cache level supports Write-Allocation.

[27:13]NumSets

Indicates the (number of sets in cache) - 1. Therefore, a value of 0 indicates 1 set in the cache. The number of sets does not have to be a power of 2.

[12:3]Associativity

Indicates the (associativity of cache) - 1. Therefore, a value of 0 indicates an associativity of 1. The associativity does not have to be a power of 2:

b0000000001

2 ways.

b0000001111

16 ways.

[2:0]LineSize

Indicates the (log2 (number of words in cache line)) - 2:

b010

16 words per line.


Table 4.47 shows the individual bit field and complete register encodings for the CCSIDR. The CSSELR determines which CCSIDR to select.

Table 4.47. Encodings of the Cache Size ID Register

CSSELRSizeComplete register encodingRegister bit field encoding
   WTWBRAWANumSetsAssociativityLineSize
0x032KB0x701FE00A01110xFF0x10x2
0x132KB0x201FE00A00100xFF0x10x2
0x2512KB0x703FE07A01110x1FF0xF0x2
1024KB0x707FE07A01110x3FF0xF0x2
2048KB0x70FFE07A01110x7FF0xF0x2
4096KB0x71FFE07A01110xFFF0xF0x2
0x3-0xF--Reserved

To access the CCSIDR, read the CP15 register with:

MRC p15, 1, <Rt>, c0, c0, 0 ; Read Cache Size ID Register
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