A.12. Cross trigger channel interface

Table A.30 shows the cross trigger channel interface signals. The value of N is one less than the number of processors in your design.

Table A.30. Cross trigger channel interface signals

SignalTypeDescription
CIHSBYPASS[3:0]Input

Cross trigger channel interface handshake bypass.

CISBYPASSInput

Cross trigger channel interface sync bypass.

CTICHIN[3:0]Input

Cross trigger channel input. Each bit represents a valid channel input:

0

Channel input inactive.

1

Channel input active.

CTICHINACK[3:0]Output

Cross trigger channel input acknowledge.

CTICHOUT[3:0]Output

Cross trigger channel output. Each bit represents a valid channel output:

0

Channel output inactive.

1

Channel output active.

CTICHOUTACK[3:0]Input

Cross trigger channel output acknowledge.

CTIEXTTRIG[N:0]Output

Cross trigger external trigger output.

CTIEXTTRIGACK[N:0]Input

Cross trigger external trigger output acknowledge.

nCTIIRQ[N:0]Output

Active-LOW cross trigger interrupt output:

0

Interrupt active.

1

Interrupt not active.


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