4.3.57. Instruction L1 Data n Register

The IL1Datan, where n is from 0 to 2, characteristics are:

Purpose

Holds the instruction side L1 array information returned by the RAMINDEX write operation. See RAM Index Register for more information.

Note

Because the data, BTB, GHB, and TLB arrays are greater than 32-bits wide, the processor contains multiple IL1Data registers, to hold the array information.

Usage constraints

The IL1Datan is:

  • a read/write register

  • Common to the Secure and Non-secure states

  • only accessible from PL1 or higher.

Configurations

Available in all configurations.

Attributes

See the register summary in Table 4.14.

Figure 4.40 shows the IL1Datan bit assignments.

Figure 4.40. IL1Datan bit assignments

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Table 4.71 shows the IL1Datan bit assignments.

Table 4.71. IL1Datan bit assignments

BitsNameFunction
[31:0]Data

Holds the instruction side L1 array information


To access the IL1Datan, read or write the CP15 registers with:

MRC p15, 0, <Rt>, c15, c0, n; Read Instruction L1 Data n Register
MCR p15, 0, <Rt>, c15, c0, n; Write Instruction L1 Data n Register

where n is 0, 1, or 2 for the Opcode_2 value of IL1Data0, IL1Data1, or IL1Data2 Register.

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