A.10.3. Miscellaneous debug signals

Table A.27 shows the miscellaneous debug signals. The value of N is one less than the number of processors in your design.

Table A.27. Miscellaneous debug signals

SignalTypeDescription
COMMRX[N:0]Output

Communications channel receive. Receive portion of Data Transfer Register full flag:

0

Empty.

1

Full.

COMMTX[N:0]Output

Communication channel transmit. Transmit portion of Data Transfer Register empty flag:

0

Full.

1

Empty.

DBGACK[N:0]Output

Debug acknowledge:

0

External debug request not acknowledged.

1

External debug request acknowledged.

DBGSWENABLE[N:0]Input

Debug software access enable:

0

Not enabled.

1

Enabled, access by the software through the Extended CP14 interface is permitted.

EDBGRQ[N:0]Input

External debug request:

0

No external debug request.

1

External debug request.

The processor treats the EDBGRQ input as level-sensitive. The EDBGRQ input must be asserted until the processor asserts DBGACK.

DBGROMADDR[39:12]Input

Specifies bits [39:12] of the ROM table physical address.

If the address cannot be determined, tie this signal off to 0.

This signal is only sampled during reset of the processor.

DBGROMADDRVInput

Valid signal for DBGROMADDR.

If the address cannot be determined, tie this signal LOW.

This signal is only sampled during reset of the processor.

DBGSELFADDR[39:17]Input

Specifies bits [39:17] of the two’s complement signed offset from the ROM table physical address to the physical address where the debug registers are memory-mapped.

If the offset cannot be determined, tie this signal off to 0.

This signal is only sampled during reset of the processor.

DBGSELFADDRVInput

Valid signal for DBGSELFADDR.If the offset cannot be determined, tie this signal LOW.

This signal is only sampled during reset of the processor.

DBGNOPWRDWN[N:0]Output

No power-down request:

0

On a power-down request, the SoC power controller powers down the processor.

1

On a power-down request, the SoC power controller does not power down the processor.

DBGPWRDWNACK[N:0]Output

Processor power-down acknowledge:

0

No acknowledge for processor power-down request.

1

Acknowledge for processor power-down request.

DBGPWRDWNREQ[N:0]Input

Processor power-down request:

0

No request for processor power down.

1

Request for processor power down.

DBGPWRUPREQ[N:0]Output

Processor power-up request:

0

No request for processor power up.

1

Request for processor power up.

DBGRSTREQ[N:0]Output

Warm reset request:

0

No request for warm reset.

1

Request for warm reset.


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