| Copyright © 2011 ARM. All rights reserved. | ARM DDI 0438D |
| Non-Confidential | ID122011 |
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The Cortex-A15 processor is delivered as synthesizable RTL. Before the processor can be used in a product, it must go through the following process:
The implementer configures and synthesizes the RTL to produce a hard macrocell. This might include integrating the cache RAMs into the design.
The integrator connects the configured design into a SoC. This includes connecting it to a memory system and peripherals.
This is the last process. The system programmer develops the SoC:
software required to configure the Cortex-A15 processor
software required to initialize the Cortex-A15 processor
application software and the SoC tests.
Each process:
can be performed by a different party
can include implementation and integration choices that affect the behavior and features of the Cortex-A15 processor.
The operation of the final device depends on:
The implementer chooses the options that affect how the RTL source files are pre-processed. These options usually include or exclude logic that can affect one or more of the area, maximum frequency, and features of the resulting macrocell.
The integrator configures some features of the Cortex-A15 processor by tying inputs to specific values. These configurations affect the start-up behavior before any software configuration is made. They can also limit the options available to the software.
The programmer configures the Cortex-A15 processor by programming particular values into registers. This affects the behavior of the Cortex-A15 processor.
This manual refers to implementation-defined features that apply to build configuration options. Reference to a feature that is included means that the appropriate build and pin configuration options have been selected. Reference to an enabled feature means that the feature has also been configured by software.
| Copyright © 2011 ARM. All rights reserved. | ARM DDI 0438D |
| Non-Confidential | ID122011 |
| PDF version | |
| Home > Introduction > Product documentation and design flow > Design flow |