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Home > Generic Interrupt Controller > GIC programmers model > Virtual interface control register summary |
The virtual interface control registers are management registers. Configuration software on the Cortex-A15 processor must ensure they are accessible only by a hypervisor, or similar software.
Table 8.12 shows the register map for the virtual interface control registers. The offsets in this table are relative to the virtual interface control registers block base address as shown in Table 8.1.
All the registers in Table 8.12 are word-accessible. Registers not described in this table are RAZ/WI.
Table 8.12. Virtual interface control register summary
Offset | Name | Type | Reset | Description |
---|---|---|---|---|
0x000 | GICH_HCR | RW | 0x00000000 | Hypervisor Control Register, see ARM Generic Interrupt Controller Architecture Specification |
0x004 | GICH_VTR | RO | 0x90000003 | VGIC Type Register |
0x008 | GICH_VMCR | RW | 0x004C0000 | Virtual Machine Control Register, see ARM Generic Interrupt Controller Architecture Specification |
0x010 | GICH_MISR | RO | 0x00000000 | Maintenance Interrupt Status Register, see ARM Generic Interrupt Controller Architecture Specification |
0x020 | GICH_EISR0 | RO | 0x00000000 | End of Interrupt Status Registers, see ARM Generic Interrupt Controller Architecture Specification |
0x030 | GICH_ELSR0 | RO | 0x0000000F | Empty List Register Status Registers, see ARM Generic Interrupt Controller Architecture Specification |
0x0F0 | GICH_APR | RW | 0x00000000 | Active Priorities Register, see ARM Generic Interrupt Controller Architecture Specification |
0x100 | GICH_LR0 | RW | 0x00000000 | List Register 0, see ARM Generic Interrupt Controller Architecture Specification |
0x104 | GICH_LR1 | RW | 0x00000000 | List Register 1, see ARM Generic Interrupt Controller Architecture Specification |
0x108 | GICH_LR2 | RW | 0x00000000 | List Register 2, see ARM Generic Interrupt Controller Architecture Specification |
0x10C | GICH_LR3 | RW | 0x00000000 | List Register 3, see ARM Generic Interrupt Controller Architecture Specification |