Cortex-A15 Technical Reference ManualRevision: r2p1
Home > Signal Descriptions > AXI interfaces > ACP signals

A.9.2. ACP signals

The following sections describe the ACP signals:

Clock and configuration signals

Table A.19 shows the clock and configuration signals for the ACP.

Table A.19. Clock and configuration signals

SignalTypeDescription
A64n128SInput

Selects 64-bit or 128-bit AXI slave bus width:

0

128-bit bus width.

1

64-bit bus width.

ACLKENSInput

AXI slave bus clock enable.

AINACTSInput

AXI slave inactive and no longer accepting requests.


Write address channel signals

Table A.20 shows the write address channel signals for the ACP.

Table A.20. Write address channel signals

SignalTypeDescription
AWADDRS[39:0]Input

Address

AWBURSTS[1:0]Input

Burst type

AWIDS[2:0]Input

Request ID

AWCACHES[3:0]Input

Cache type

AWLENS[3:0]Input

Burst length

AWPROTS[2:0]Input

Protection type

AWREADYSOutput

Address ready

AWSIZES[2:0]Input

Burst size

AWUSERS[5:0]Input

User signals:

  • [5:2] Inner attributes:

    b0000

    Strongly-ordered.

    b0001

    Device.

    b0011

    Normal Memory Non-Cacheable.

    b0110

    Write-Through.

    b0111

    Write-Back No Write-Allocate.

    b1111

    Write-Back Write-Allocate.

  • [1] Inner shareable

  • [0] Outer shareable.

AWVALIDSInput

Address valid


Write data channel signals

Table A.21 shows the write data channel signals for the ACP.

Table A.21. Write data channel signals

SignalTypeDescription
WDATAS[127:0]Input

Write data

WLASTSInput

Write last

WREADYSOutput

Write ready

WSTRBS[15:0]Input

Write strobes

WVALIDSInput

Write valid


Write response channel signals

Table A.22 shows the write response channel signals for the ACP.

Table A.22. Write response channel signals

SignalTypeDescription
BIDS[2:0]Output

Response ID

BREADYSInput

Response ready

BRESPS[1:0]Output

Write response

BVALIDSOutput

Response valid


Read address channel signals

Table A.23 shows the read address channel signals for the ACP.

Table A.23. Read address channel signals

SignalTypeDescription
ARADDRS[39:0]Input

Address

ARBURSTS[1:0]Input

Burst type

ARCACHES[3:0]Input

Cache type

ARIDS[2:0]Input

Request ID

ARLENS[3:0]Input

Burst length

ARPROTS[2:0]Input

Protection type

ARREADYSOutput

Address ready

ARSIZES[2:0]Input

Burst size

ARUSERS[5:0]Input

User signals:

  • [5:2] Inner attributes:

    b0000

    Strongly-ordered.

    b0001

    Device.

    b0011

    Normal Memory Non-Cacheable.

    b0110

    Write-Through.

    b1011

    Write-Back No Read-Allocate.

    b1111

    Write-Back Read-Write-Allocate.

  • [1] Inner shareable

  • [0] Outer shareable.

ARVALIDSInput

Address valid


Read data channel signals

Table A.24 shows the read data channel signals for the ACP.

Table A.24. Read data channel signals

SignalTypeDescription
RDATAS[127:0]Output

Read data

RIDS[2:0]Output

Read ID

RLASTSOutput

Read last

RREADYSInput

Read ready

RRESPS[1:0]Output

Read response

RVALIDSOutput

Read valid


Copyright © 2011 ARM. All rights reserved.ARM DDI 0438D
Non-ConfidentialID122011
PDF file icon  PDF version
Home > Signal Descriptions > AXI interfaces > ACP signals