4.3.15. Instruction Set Attribute Register 0

The ID_ISAR0 characteristics are:

Purpose

Provides information about the instruction set that the processor supports.

Usage constraints

The ID_ISAR0 is:

  • a read-only register

  • Common to the Secure and Non-secure states

  • only accessible from PL1 or higher.

Configurations

Available in all configurations.

Attributes

See the register summary in Table 4.2.

Figure 4.13 shows the ID_ISAR0 bit assignments.

Figure 4.13. ID_ISAR0 bit assignments

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Table 4.41 shows the ID_ISAR0 bit assignments.

Table 4.41. ID_ISAR0 bit assignments

BitsNameFunction
[31:28]-

Reserved, RAZ.

[27:24]Divide_instrs

Indicates support for Divide instructions.

0x2

Processor supports:

  • SDIV and UDIV in the Thumb instruction set

  • SDIV and UDIV in the ARM instruction set.

[23:20]Debug_instrs

Indicates the supported Debug instructions:

0x1

Processor supports BKPT instruction.

[19:16]Coproc_instrs

Indicates the supported Coprocessor instructions:

0x0

None supported, except for separately attributed architectures including CP15, CP14, and Advanced SIMD and VFP.

[15:12]CmpBranch_instrs

Indicates the supported combined Compare and Branch instructions in the Thumb instruction set:

0x1

Processor supports CBNZ and CBZ instructions.

[11:8]Bitfield_instrs

Indicates the supported BifField instructions:

0x1

Processor supports BFC, BFI, SBFX, and UBFX instructions.

[7:4]BitCount_instrs

Indicates the supported Bit Counting instructions:

0x1

Processor supports CLZ instruction.

[3:0]Swap_instrs

Indicates the supported Swap instructions in the ARM instruction set:

0x0

Not supported.


To access the ID_ISAR0, read the CP15 register with:

MRC p15, 0, <Rt>, c0, c2, 0 ; Read Instruction Set Attribute Register 0
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