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| Non-Confidential | ID122011 |
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Table A.31 shows the performance monitoring signals. In this table, the value of N is one less than the number of processors and the value x represents processor 0, 1, 2, or 3 in your design.
Table A.31. Performance monitoring signals
| Signal | Type | Description |
|---|---|---|
| nPMUIRQ[N:0] | Output | PMU interrupt signal |
| PMUEVENTx[24:0] | Output | PMU event bus |
| Copyright © 2011 ARM. All rights reserved. | ARM DDI 0438D |
| Non-Confidential | ID122011 |
| PDF version | |
| Home > Signal Descriptions > PMU signals |