4.3.44. Hyp Auxiliary Data Fault Syndrome Register

The HADFSR characteristics is:

Purpose

Holds syndrome information for the asynchronous L1 and L2 ECC double-bit errors that occurred in Hyp mode.

Usage constraints

The HADFSR is:

  • a read/write register

  • only accessible from Hyp mode or from Monitor mode when SCR.NS is 1.

Configurations

Available in all configurations.

Attributes

See the register summary in Table 4.6.

Figure 4.36 shows the HADFSR bit assignments.

Figure 4.36. HADFSR bit assignments

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Table 4.67 shows the HADFSR bit assignments.

Table 4.67. HADFSR bit assignments

BitsNameFunction
[31]Valid

Valid bit. This field indicates that an L1 or L2 ECC double-bit error has occurred:

0

No L1 or L2 ECC double-bit error occurred.

1

An L1 or L2 ECC double-bit error occurred.

[30:24]RAM ID

RAM Identifier. This field indicates which RAM, the L1 ECC double-bit error occurred in:

0x8

L1 tag RAM.

0x9

L1 data RAM.

If an L2 ECC double-bit error occurred, this field returns 0.

[23]L2 Error

L2 Error bit. This field indicates an L2 ECC double-bit error occurred:

0

No L2 ECC double-bit error occurred.

1

An L2 ECC double-bit error occurred.

[22:18]Bank/Way

Bank/Way bit. This field indicates which bank or way of the RAM, the L1 ECC double-bit error occurred in. If an L2 ECC double-bit error occurred, this field returns 0.

[17:0]Index

Index. This field indicates the index address of the RAM, the L1 ECC double-bit error occurred in. If an L2 ECC double-bit error occurred, this field returns 0.


To access the HADFSR, read or write the CP15 register with:

MRC p15, 4, <Rt>, c5, c1, 0; Read Hyp Auxiliary Data Fault Status Syndrome Register
MCR p15, 4, <Rt>, c5, c1, 0; Write Hyp Auxiliary Data Fault Status Syndrome Register
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