4.3.2. Cache Type Register

The CTR characteristics are:

Purpose

Provides information about the architecture of the caches.

Usage constraints

The CTR is:

  • a read-only register

  • Common to the Secure and Non-secure states

  • only accessible from PL1 or higher.

Configurations

Available in all configurations.

Attributes

See the register summary in Table 4.2.

Figure 4.2 shows the CTR bit assignments.

Figure 4.2. CTR bit assignments

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Table 4.30 shows the CTR bit assignments.

Table 4.30. CTR bit assignments

BitsNameFunction
[31:29]Format

Indicates the implemented CTR format:

b100

ARMv7 format.

[28]-

Reserved, RAZ.

[27:24]CWG

Cache Writeback Granule. Log2 of the number of words of the maximum size of memory that can be overwritten as a result of the eviction of a cache entry that has had a memory location in it modified:

0x4

Cache writeback granule size is 16 words.

[23:20]ERG

Exclusives Reservation Granule. Log2 of the number of words of the maximum size of the reservation granule that has been implemented for the Load-Exclusive and Store-Exclusive instructions:

0x4

Exclusive reservation granule size is 16 words.

[19:16]DminLine

Log2 of the number of words in the smallest cache line of all the data and unified caches that the processor controls:

0x4

Smallest data cache line size is 16 words.

[15:14]L1lp

Level 1 instruction cache policy. Indicates the indexing and tagging policy for the L1 instruction cache:

b11

Physical index, physical tag.

[13:4]-

Reserved, RAZ.

[3:0]IminLine

Log2 of the number of words in the smallest cache line of all the instruction caches that the processor controls. The primary input IMINLN defines the reset value:

0x3

Smallest instruction cache line size is 8 words, IMINLN is set to 0.

0x4

Smallest instruction cache line size is 16 words, IMINLN is set to 1.


To access the CTR, read the CP15 register with:

MRC p15, 0, <Rt>, c0, c0, 1; Read Cache Type Register
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