4.3.64. L2 Memory Error Syndrome Register

The L2MERRSR characteristics are:

Purpose

Holds the number of memory errors that have occurred in the following L2 RAMs:

  • L2 tag RAM

  • L2 data RAM

  • L2 snoop tag RAM

  • L2 dirty RAM.

Usage constraints

The L2MERRSR:

  • is a 64-bit read/write register

  • is Common to the Secure and Non-Secure states

  • is only accessible from PL1 or higher

  • a write of any value to the register updates the register to 0.

Configurations

Available in all configurations.

Attributes

See the register summary in Table 4.15.

Figure 4.63 shows the L2MERRSR bit assignments.

Figure 4.63. L2MERRSR bit assignments

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Table 4.78 shows the L2MERRSR bit assignments.

Table 4.78. L2MERRSR bit assignments

BitsNameFunction
[63]Fatal

Fatal bit. This bit is set to 1 on the first memory error that caused a data abort. It is a sticky bit so that after it is set, it remains set until the register is written.

The reset value is 0.

[62:48]-

Reserved, RAZ/WI.

[47:40]

Other error count

This field is set to 0 on the first memory error and is incremented on any memory error that does not match the RAMID, bank, way, or index information in this register while the sticky Valid bit is set.

The reset value is 0.

[39:32]Repeat error count

This field is set to 0 on the first memory error and is incremented on any memory error that exactly matches the RAMID, bank, way or index information in this register while the sticky Valid bit is set.

The reset value is 0.

[31]Valid

Valid bit. This bit is set to 1 on the first memory error. It is a sticky bit so that after it is set, it remains set until the register is written.

The reset value is 0.

[30:24]RAMID

RAM Identifier. Indicates the RAM where the first memory error occurred:

0x10

L2 tag RAM.

0x11

L2 data RAM.

0x12

L2 snoop tag RAM.

0x14

L2 dirty RAM.

[23:22]-

Reserved, RAZ/WI.

[21:18]CPUID/Way

Indicates which processor and way of the RAM where the first memory error occurred.

For L2 tag, data, and dirty RAMs, bits [21:18] indicate one of 16 ways, from way 0 to way 15.

b0000

CPU0 tag, way 0.

b0001

CPU0 tag, way 1.

b0010

CPU1 tag, way 0.

b0011

CPU1 tag, way 1.

b0100

CPU2 tag, way 0.

b0101

CPU2 tag, way 1.

b0110

CPU3 tag, way 0.

b0111

CPU3 tag, way 1.

For L2 snoop tag RAM:

  • bits [20:19] indicate which processor of the L1 tag RAM

  • bit [18] indicates which way of the tag RAM.

[17:0]Index

Indicates the index address of the first memory error.


Note

  • If two or more memory errors in the same RAM occur in the same cycle, only one error is reported.

  • If two or more first memory error events from different RAMs occur in the same cycle, one of the errors is selected arbitrarily, while the Other error count field is only incremented by one.

  • If two or more memory error events from different RAMs, that do not match the RAMID, bank, way, or index information in this register while the sticky Valid bit is set, occur in the same cycle, the Other error count field is only incremented by one.

To access the L2MERRSR, read or write the CP15 register with:

MRRC p15, 1, <Rt>, <Rt2>, c15;  Read L2 Memory Error Syndrome Register
MCCR p15, 1, <Rt>, <Rt2>, c15;  Write L2 Memory Error Syndrome Register
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