A.8. Power management signals

Table A.7 shows the power management signals. The value of N is one less than the number of processors in your design.

Table A.7. Power management signals

SignalTypeDescription
nISOLATECPU[N:0][a]Input

Individual processor clamp control:

0

Processor clamp active.

1

Processor clamp not active.

nISOLATECX[N:0][a]Input

Individual NEON and VFP clamp control:

0

NEON and VFP clamp active.

1

NEON and VFP clamp not active.

nISOLATEL2MISC[a]Input

L2 control, GIC, and Timer clamp control:

0

L2 control, GIC, and Timer clamp active.

1

L2 control, GIC, and Timer clamp not active.

nISOLATEPDBG[a]Input

Debug, CTI, and CTM in the PCLKDBG domain clamp control:

0

Debug, CTI, and CTM in the PCLKDBG domain clamp active.

1

Debug, CTI, and CTM in the PCLKDBG domain clamp not active.

nPWRUPCPU[N:0][a]Input

Individual processor power switch enable:

0

Processor power switch enabled.

1

Processor power switch not enabled.

nPWRUPCX[N:0][a]Input

Individual NEON and VFP power switch enable:

0

NEON and VFP power switch enabled.

1

NEON and VFP power switch not enabled.

nPWRUPL2MISC[a]Input

L2 control, GIC, and Timer power switch enable:

0

L2 control, GIC, and Timer power switch enabled.

1

L2 control, GIC, and Timer power switch not enabled.

nPWRUPL2RAM[a]Input

L2 tag bank RAMs power switch enable:

0

L2 tag bank RAMs power switch enabled.

1

L2 tag bank RAMs power switch not enabled.

nPWRUPPDBG[a]Input

Debug, CTI, and CTM in the PCLKDBG domain power switch enable:

0

Debug, CTI, and CTM in the PCLKDBG domain power switch enabled.

1

Debug, CTI, and CTM in the PCLKDBG domain power switch not enabled.

[a] This signal is not present if the Cortex-A15 processor is configured without the power switch and clamp control signals.


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