Cortex-A15 Technical Reference ManualRevision: r2p1
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4.3.12. Memory Model Feature Register 1

The ID_MMFR1 characteristics are:

Purpose

Provides information about the implemented memory model and memory management support.

Usage constraints

The ID_MMFR1 is:

  • a read-only register

  • Common to the Secure and Non-secure states

  • only accessible from PL1 or higher.

Configurations

Available in all configurations.

Attributes

See the register summary in Table 4.2.

Figure 4.10 shows the ID_MMFR1 bit assignments.

Figure 4.10. ID_MMFR1 bit assignments

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Table 4.38 shows the ID_MMFR1 bit assignments.

Table 4.38. ID_MMFR1 bit assignments

BitsNameFunction
[31:28]Branch predictor

Indicates branch predictor management requirements.

0x2

Branch predictor requires flushing on:

  • enabling or disabling the MMU

  • writing new data to instruction locations

  • writing new mappings to the translation tables.

  • any change to the TTBR0, TTBR1, or TTBCR registers without a corresponding change to the FCSE ProcessID or ContextID.

[27:24]L1 cache test and clean

Indicates the supported L1 data cache test and clean operations, for Harvard or unified cache implementation:

0x0

Not supported.

[23:20]L1 unified cache

Indicates the supported entire L1 cache maintenance operations, for a unified cache implementation:

0x0

Not supported.

[19:16]L1 Harvard cache

Indicates the supported entire L1 cache maintenance operations, for a Harvard cache implementation:

0x0

Not supported.

[15:12]L1 unified cache set/way

Indicates the supported L1 cache line maintenance operations by set/way, for a unified cache implementation:

0x0

Not supported.

[11:8]L1 Harvard cache set/way

Indicates the supported L1 cache line maintenance operations by set/way, for a Harvard cache implementation:

0x0

Not supported.

[7:4]L1 unified cache VA

Indicates the supported L1 cache line maintenance operations by MVA, for a unified cache implementation:

0x0

Not supported.

[3:0]L1 Harvard cache VA

Indicates the supported L1 cache line maintenance operations by MVA, for a Harvard cache implementation:

0x0

Not supported.


To access the ID_MMFR1, read the CP15 register with:

MRC p15, 0, <Rt>, c0, c1, 5; Read Memory Model Feature Register 1
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