4.3.63. CPU Memory Error Syndrome Register

The CPUMERRSR characteristics are:

Purpose

Holds the number of memory errors that have occurred in the following L1 and L2 RAMs:

  • L1-I tag RAM

  • L1-I data RAM

  • L1-I BTB RAM

  • L1-D tag RAM

  • L1-D data RAM

  • L2 TLB RAM.

Usage constraints

The CPUMERRSR:

  • is a 64-bit read/write register

  • is Common to the Secure and Non-Secure states

  • is only accessible from PL1 or higher

  • a write of any value to the register updates the register to 0x0.

Configurations

Available in all configurations.

Attributes

See the register summary in Table 4.15.

Figure 4.62 shows the CPUMERRSR bit assignments.

Figure 4.62. CPUMERRSR bit assignments

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Table 4.77 shows the CPUMERRSR bit assignments.

Table 4.77. CPUMERRSR bit assignments

BitsNameFunction
[63]Fatal

Fatal bit. This bit is set to 1 on the first memory error that caused a data abort. It is a sticky bit so that after it is set, it remains set until the register is written.

The reset value is 0.

[62:48]-

Reserved, RAZ/WI.

[47:40]

Other error count

This field is set to 0 on the first memory error and is incremented on any memory error that does not match the RAMID, bank, way, or index information in this register while the sticky Valid bit is set.

The reset value is 0.

[39:32]Repeat error count

This field is set to 0 on the first memory error and is incremented on any memory error that exactly matches the RAMID, bank, way or index information in this register while the sticky Valid bit is set.

The reset value is 0.

[31]Valid

Valid bit. This bit is set to 1 on the first memory error. It is a sticky bit so that after it is set, it remains set until the register is written.

The reset value is 0.

[30:24]RAMID

RAM Identifier. Indicates the RAM, the first memory error occurred in:

0x00

L1-I tag RAM.

0x01

L1-I data RAM.

0x02

L1-I BTB RAM.

0x08

L1-D tag RAM.

0x09

L1-D data RAM.

0x18

L2 TLB RAM.

[23]-

Reserved, RAZ/WI.

[22:18]Bank/Way

Indicates the bank or way of the RAM where the first memory error occurred.

[17:0]Index

Indicates the index address of the first memory error.


Note

  • If two or more memory errors in the same RAM occur in the same cycle, only one error is reported.

  • If two or more first memory error events from different RAMs occur in the same cycle, one of the errors is selected arbitrarily, while the Other error count field is only incremented by one.

  • If two or more memory error events from different RAMs, that do not match the RAMID, bank, way, or index information in this register while the sticky Valid bit is set, occur in the same cycle, the Other error count field is only incremented by one.

To access the CPUMERRSR, read or write the CP15 register with:

MRRC p15, 0, <Rt>, <Rt2>, c15;  Read CPU Memory Error Syndrome Register
MCCR p15, 0, <Rt>, <Rt2>, c15;  Write CPU Memory Error Syndrome Register
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