| Copyright © 2011 ARM. All rights reserved. | ARM DDI 0438D |
| Non-Confidential | ID122011 |
 PDF version | |
| Home > System Control > Register descriptions > Translation Table Base Register 0 and Register 1 |
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| Home > System Control > Register descriptions > Translation Table Base Register 0 and Register 1 | |||
The processor does not use any implementation-defined bits in the 32-bit TTBR0 and TTBR1 format, so these bits are UNK/SBZP.
| Copyright © 2011 ARM. All rights reserved. | ARM DDI 0438D |
| Non-Confidential | ID122011 |
| PDF version | |
| Home > System Control > Register descriptions > Translation Table Base Register 0 and Register 1 |