Cortex-A15 Technical Reference Manual: 4.3.34. Hyp Debug Configuration Register

4.3.34. Hyp Debug Configuration Register

The HDCR characteristics are:

Purpose

Controls the trapping to Hyp mode of Non-secure accesses, at PL1 or lower, to functions provided by the debug and trace architectures.

Usage constraints

The HDCR is:

a read/write register
only accessible from Hyp mode or from Monitor mode when SCR.NS is 1.

Configurations

Available in all configurations.

Attributes

See the register summary in Table 4.3.

Figure 4.29 shows the HDCR bit assignments.

Figure 4.29. HDCR bit assignments

Table 4.58 shows the HDCR bit assignments.

Table 4.58. HDCR bit assignments

Bits	Name	Function
[31:12]	-	Reserved, UNK/SBZP.
[11]	TDRA	Trap Debug ROM Access: 0 Has no effect on Debug ROM accesses. 1 Trap valid Non-secure Debug ROM accesses to Hyp mode. When this bit is set to 1, any valid Non-secure access to the following registers is trapped to Hyp mode: DBGDRAR DBGDSAR DBGOSDLR DBGPRCR. If this bit is set to 0 when TDA is set to 1, behavior is unpredictable. This bit resets to 0.
[10]	TDOSA	Trap Debug OS-related register Access: 0 Has no effect on accesses to CP14 Debug registers. 1 Trap valid Non-secure accesses to CP14 OS-related Debug registers to Hyp mode. When this bit is set to 1, any valid Non-secure CP14 access to the following OS-related Debug registers is trapped to Hyp mode. DBGOSLSR DBGOSLAR DBGOSDLR DBGPRCR. If this bit is set to 0 when TDE is set to 1, behavior is unpredictable. This bit resets to 0.
[9]	TDA	Trap Debug Access: 0 Has no effect on accesses to CP14 Debug registers. 1 Trap valid Non-secure accesses to CP14 Debug registers to Hyp mode. When this bit is set to 1, any valid Non-secure access to the CP14 Debug registers, other than the registers trapped by the TDRA and TDOSA bits, is trapped to Hyp mode. If this bit is set to 0 when TDE is set to 1, behavior is unpredictable. This bit resets to 0.
[8]	TDE	Trap Debug Exceptions: 0 Has no effect on Debug exceptions. 1 Trap valid Non-secure Debug exceptions to Hyp mode. When this bit is set to 1, any Debug exception taken in Non-secure state is trapped to Hyp mode. When this bit is set to 1, the TDRA, TDOSA, and TDA bits must all be set to 1, otherwise behavior is unpredictable. This bit resets to 0.
[7]	HPME	Hypervisor Performance Monitors Enable: 0 Hyp mode Performance Monitors counters disabled. 1 Hyp mode Performance Monitors counters enabled. When this bit is set to 1, access to the Performance Monitors counters that are reserved for use from Hyp mode is enabled. For more information, see the description of the HPMN field. The reset value of this bit is unknown.
[6]	TPM	Trap Performance Monitors accesses: 0 Has no effect on Performance Monitors accesses. 1 Trap valid Non-secure Performance Monitors accesses to Hyp mode. When this bit is set to 1, any valid Non-secure access to the Performance Monitors registers is trapped to Hyp mode. This bit resets to 0. See the ARM Architecture Reference Manual for more information.
[5]	TPMCR	Trap Performance Monitor Control Register accesses: 0 Has no effect on PMCR accesses. 1 Trap valid Non-secure PMCR accesses to Hyp mode. When this bit is set to 1, any valid Non-secure access to the PMCR is trapped to Hyp mode. This bit resets to 0. See the ARM Architecture Reference Manual for more information.
[4:0]	HPMN	Defines the number of Performance Monitors counters that are accessible from Non-secure PL1 modes, and from Non-secure PL0 modes if unprivileged access is enabled. In Non-secure state, HPMN divides the Performance Monitors counters as follows: If PMXEVCNTR is accessing Performance Monitors counter n then, in Non-secure state: If n is in the range 0 ≤n<HPMN, the counter is accessible from PL1 and PL2, and from PL0 if unprivileged access to the counters is enabled. If n is in the range HPMN≤n<PMCR.N, the counter is accessible only from PL2. The HPME bit enables access to the counters in this range. Behavior of the Performance Monitors counters is unpredictable if this field is set to a value greater than PMCR.N. This field resets to `0x6`, which is the value of PMCR.N.

To access the HDCR, read or write the CP15 register with:

MRC p15, 4, <Rt>, c1, c1, 1; Read Hyp Debug Configuration Register

MCR p15, 4, <Rt>, c1, c1, 1; Write Hyp Debug Configuration Register

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