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Table A.2 shows the reset and reset control signals. The value of N is one less than the number of processors in your design.
Table A.2. Reset signals
Signal | Type | Description |
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nCPUPORESET[N:0] | Input | Individual processor resets:
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nCORERESET[N:0] | Input | Individual processor reset excluding Debug and PTM:
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nCXRESET[N:0] | Input | Individual processor NEON and VFP resets:
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nDBGRESET[N:0] | Input | Individual processor Debug and PTM resets:
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nL2RESET | Input | L2 reset:
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L2RSTDISABLE | Input | L2 cache hardware reset disable:
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See Clocking and resets for more information.