A.5. Generic Interrupt Controller signals

Table A.4 shows the GIC signals. The value of N is one less than the number of processors in your design.

Table A.4. GIC signals

SignalTypeDescription
CFGSDISABLE[a]Input

Disable write access to some secure GIC registers.

IRQS[n:0][b]Input

Interrupt request input lines for the GIC where n can be 31, 63, up to 223 by increments of 32.

nIRQ[N:0]Input

Individual processor IRQ request input lines. Active-LOW, interrupt request:

0

Activate interrupt.

1

Do not activate interrupt.

The processor treats the nIRQ input as level-sensitive. The nIRQ input must be asserted until the processor acknowledges the interrupt.

nFIQ[N:0]Input

Individual processor FIQ request input line. Active-LOW, FIQ request:

0

Activate FIQ request.

1

Do not activate FIQ request.

The processor treats the nFIQ input as level-sensitive. The nFIQ input must be asserted until the processor acknowledges the interrupt.

nVIRQ[N:0]Input

Individual processor virtual IRQ request input lines. Active-LOW, interrupt request:

0

Activate virtual IRQ request.

1

Do not activate virtual IRQ request.

The processor treats the nVIRQ input as level-sensitive. The nVIRQ input must be asserted until the processor acknowledges the interrupt. If the Cortex-A15 processor is configured to include the GIC, and the GIC is used, the input pins nVIRQ and nVFIQ must be tied off to HIGH. If the processor is configured to include the GIC, and the GIC is not used, the input pins nVIRQ and nVFIQ can be driven by an external GIC in the SoC.

See GIC configuration for more information.

nVFIQ[N:0]Input

Individual processor virtual FIQ request input lines. Active-LOW, virtual FIQ request:

0

Activate virtual FIQ request.

1

Do not activate virtual FIQ request.

The processor treats the nVFIQ input as level-sensitive. The nVFIQ input must be asserted until the processor acknowledges the interrupt. If the Cortex-A15 processor is configured to include the GIC, and the GIC is used, the input pins nVIRQ and nVFIQ must be tied off to HIGH. If the processor is configured to include the GIC, and the GIC is not used, the input pins nVIRQ and nVFIQ can be driven by an external GIC in the SoC.

See GIC configuration for more information.

nIRQOUT[N:0][a]Output

Active-LOW output of individual processor nIRQ from the GIC.

For use when processors are powered off and interrupts from the GIC are routed to an external power controller.

nFIQOUT[N:0][a]Output

Active-LOW output of individual processor nFIQ from the GIC.

For use when processors are powered off and interrupts from the GIC are routed to an external power controller.

PERIPHBASE[39:15]Input

Specifies the base address for the GIC registers.This value is sampled into the CP15 Configuration Base Address Register (CBAR) at reset. See Configuration Base Address Register.

PERIPHCLKEN[a]Input

GIC clock enable.

[a] This signal is not present if the Cortex-A15 processor is configured without the GIC.

[b] This signal is not present if the Cortex-A15 processor is configured with zero Shared Peripheral Interrupt (SPI) inputs or without the GIC.


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