| Copyright © 2011 ARM. All rights reserved. | ARM DDI 0438D |
| Non-Confidential | ID122011 |
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The Cortex-A15 processor supports the following ACE configurations:
The AXI3 mode configuration has the following key features:
AXI3-compliant
ReadNoSnoop is the only AR channel command issued
WriteNoSnoop is the only AW channel command issued
no cache maintenance, DVM operations, or barriers issued on the AR channel
no request sent to the processor on the snoop AC channel.
The ACE non-coherent, no L3 cache configuration has the following key features:
ACE-compliant with no coherent masters on the ACE
no L3 cache external to the processor
ReadNoSnoop and barriers are the only AR channel commands issued
WriteNoSnoop and barriers are the only AW channel commands issued
no cache maintenance or DVM operations issued on the AR channel
no request sent to the processor on the snoop AC channel.
The ACE non-coherent, with L3 cache configuration has the following key features:
ACE-compliant with no coherent masters on the ACE
L3 cache external to the processor
ReadNoSnoop, barriers, and cache maintenance are the only AR channel commands issued
WriteNoSnoop and barriers are the only AW channel commands issued
no DVM operations issued on the AR channel
no request sent to the processor on the snoop AC channel.
The ACE outer coherent configuration has the following key features:
ACE-compliant with coherent masters on the ACE
the coherent masters can share memory in the outer shareable domain only
L3 cache external to the processor
the AR channel can issue any command, except for DVM operations
the AW channel can issue any command
the system can send snoop commands for outer shareable memory regions on the snoop AC channel.
The ACE inner coherent configuration has the following key features:
ACE-compliant with coherent masters on the ACE
the coherent masters can share memory in the inner or outer shareable domains
L3 cache external to the processor
the AR channel can issue any command, including DVM operations
the AW channel can issue any command
the system can send DVM or snoop commands for any shareable memory region on the snoop AC channel.
| Copyright © 2011 ARM. All rights reserved. | ARM DDI 0438D |
| Non-Confidential | ID122011 |
| PDF version | |
| Home > Level 2 Memory System > ACE > ACE configurations |