7.5. ACE

AXI Coherency Extensions (ACE) is an extension to the AXI protocol and provides the following enhancements:

The width of the AXI read and write channels can be configured for a 64-bit or 128-bit interface.

ACE supports 1:1 clock ratios with respect to the processor clock. It can also run at any integer multiple of the processor clock N:1.


  • The Cortex-A15 processor does not support a 64-bit ACE with a 128-bit ACP.

  • No read or write request from a Cortex-A15 ACE master port can cross a 64-byte aligned boundary. The request, including non-cacheable, is always broken up.

This section describes ACE in:

Copyright © 2011 ARM. All rights reserved.ARM DDI 0438D