Cortex-A15 Technical Reference ManualRevision: r2p1
Home > System Control > Register descriptions > TLB Type Register

4.3.4. TLB Type Register

The TLBTR characteristics are:

Purpose

Provides information about the TLB implementation.

Usage constraints

The TLBTR is:

  • a read-only register

  • Common to the Secure and Non-secure states

  • only accessible from PL1 or higher.

Configurations

Available in all configurations.

Attributes

See the register summary in Table 4.2.

Figure 4.3 shows the TLBTR bit assignments.

Figure 4.3. TLBTR bit assignments

To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


Table 4.31 shows the TLBTR bit assignments.

Table 4.31. TLBTR bit assignments

BitsNameFunction
[31:1]-Reserved, RAZ.
[0]nU

Not Unified. Indicates whether the implementation has a unified TLB:

0x0

Processor has a unified TLB.


To access the TLBTR, read the CP15 register with:

MRC p15, 0, <Rt>, c0, c0, 3; Read TLB Type Register
Copyright © 2011 ARM. All rights reserved.ARM DDI 0438D
Non-ConfidentialID122011
PDF file icon  PDF version
Home > System Control > Register descriptions > TLB Type Register