9.2. Generic Timer functional description

The Cortex-A15 Generic Timer includes:

The four timers are of the following:

The Cortex-A15 processor does not include the system counter which resides in the SoC. The system counter value is distributed to the Cortex-A15 processor with a synchronous binary encoded 64-bit bus, CNTVALUEB[63:0].

Each timer provides an active-LOW interrupt output that is an external pin to the SoC and is sent to the GIC as a Private Peripheral Interrupt (PPI). See Interrupt sources for the ID and PPI allocation of the Timer interrupts.

Table 9.1 shows the signals that are the external interrupt output pins.

Table 9.1. Generic Timer signals

nCNTNSIRQ[n:0]Non-secure PL1 physical timer event
nCNTSIRQ[n:0]Secure PL1 physical timer event
nCNTHPIRQ[n:0]Non-secure PL2 physical timer event
nCNTVIRQ[n:0]Virtual timer event

[a] n is the number of processors present in the MPCore device, minus one.

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