4.3.42. Auxiliary Data Fault Status Register

The ADFSR characteristics are:

Purpose

Holds the information about asynchronous L1 and L2 ECC double-bit errors.

Usage constraints

The ADFSR is:

  • a read/write register

  • Banked for Secure and Non-secure states

  • accessible from PL1 or higher.

Configurations

Available in all configurations.

Attributes

See the register summary in Table 4.6.

Figure 4.35 shows the ADFSR bit assignments.

Figure 4.35. ADFSR bit assignments

To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


Table 4.66 shows the ADFSR bit assignments.

Table 4.66. ADFSR bit assignments

BitsNameFunction
[31]Valid

Valid bit. This field indicates that an L1 or L2 ECC double-bit error has occurred:

0

No L1 or L2 ECC double-bit error occurred.

1

An L1 or L2 ECC double-bit error occurred.

[30:24]RAM ID

RAM Identifier. This field indicates which RAM, the L1 ECC double-bit error occurred in:

0x8

L1 tag RAM.

0x9

L1 data RAM.

If an L2 ECC double-bit error occurred, this field returns 0.

[23]L2 Error

L2 Error bit. This field indicates an L2 ECC double-bit error occurred:

0

No L2 ECC double-bit error occurred.

1

An L2 ECC double-bit error occurred.

[22:18]Bank/Way

Bank/Way bit. This field indicates which bank or way of the RAM, the L1 ECC double-bit error occurred in. If an L2 ECC double-bit error occurred, this field returns 0.

[17:0]Index

Index. This field indicates the index address of the RAM, the L1 ECC double-bit error occurred in. If an L2 ECC double-bit error occurred, this field returns 0.


To access the ADFSR, read or write the CP15 register with:

MRC p15, 0, <Rt>, c5, c1, 0; Read Auxiliary Data Fault Status Register
MCR p15, 0, <Rt>, c5, c1, 0; Write Auxiliary Data Fault Status Register
Copyright © 2011 ARM. All rights reserved.ARM DDI 0438D
Non-ConfidentialID122011