7.4. L2 cache prefetcher

The Cortex-A15 processor includes a hardware L2 auto-prefetcher. Some of the key features are:

You can program the L2 Prefetch Control Register, see L2 Prefetch Control Register, to indicate the maximum number of prefetches to be allocated in the PRQ on the following:

The programmed distance is also used as the skip distance for any load-store or instruction fetch read with a stride match that hits in the L2 cache. In these cases, a single prefetch request is allocate in the PRQ as:

prefetch address = current address + (stride x programmed distance)


The stride for an instruction fetch access is always one cache line.

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