6.4.1. Behavior for different memory types

The L1 data memory system uses memory attributes from the MMU to determine how to behave for memory transactions to regions of memory. See Chapter 5 Memory Management Unit for more information.

The L1 data memory system uses the following memory types:


Some attribute combinations are only available if the LPAE page table format is used.

Table 6.1 shows the memory attribute combinations available.

Table 6.1. Memory attribute combinations

Memory typeCacheabilityAllocation policyCortex-A15 processor behavior
NormalNon-Cacheable-Normal Non-Cacheable
NormalWrite-ThroughRead-AllocateWrite-Through No-Allocate
NormalWrite-ThroughWrite-AllocateWrite-Through No-Allocate
NormalWrite-ThroughRead-Write-AllocateWrite-Through No-ALlocate
NormalWrite-ThroughNo-AllocateWrite-Through No-Allocate
NormalWrite-BackRead-AllocateWrite-Back Read-Write-Allocate
NormalWrite-BackWrite-AllocateWrite-Back Read-Write-Allocate
NormalWrite-BackRead-Write-AllocateWrite-Back Read-Write-Allocate
NormalWrite-BackNo-AllocateWrite-Back No-Allocate

The L1 and L2 data memory system uses the inner memory attributes from the MMU to determine its behavior.

If any memory instruction crosses a 4KB page boundary between two pages with different memory types such as Normal or Strongly-ordered, the result is Unpredictable and an abort might be triggered or incorrect data delivered.

If any given physical address is mapped to virtual addresses with different memory types or different cacheability such as Non-Cacheable, Write-Through, or Write-Back, the result is Unpredictable. This can occur if two virtual addresses are mapped to the same physical address at the same time with different memory type or cacheability, or if the same virtual address has its memory type or cacheability changed over time without the appropriate cache cleaning or barriers.

Write-Back Read-Write-Allocate

This is expected to be the most common and highest performance memory type. Any read or write to this memory type searches the cache to determine if the line is resident. If it is, the line is read or updated. A store that hits a Write-Back cache line does not update main memory.

If the required cache line is not in the cache, one or more cache lines is requested from the L2 cache. The L2 cache can obtain the lines from its cache, from another coherent L1 cache, or from memory. The line is then placed in the L1 cache, and the operation completes from the L1 cache.

Write-Back No-Allocate

Use Write-Back No-Allocate memory to access data that might be in the cache because other virtual pages that are mapped to the same physical address are Write-Back Read-Write-Allocate. Write-Back No-Allocate memory is used to avoid polluting the caches when accessing large memory structures that are used only one time. The cache is searched and the correct data is delivered or updated if the data resides in one of the caches. However, if the request misses the L1 or L2 cache, the line is not allocated into that cache. For a read that misses all caches, the required data is read to satisfy the memory request, but the line is not added to the cache. For a write that misses in all caches, the modified bytes are updated in memory.


The No-Allocate allocation hint is only a performance hint. The Cortex-A15 processor might in some cases, allocate Write-Back No-Allocate lines into the L1 data cache or the L2.


The Cortex A15 processor memory system treats all Write-Through pages as Write-Through No-Allocate. This means that no cache line from any Write-Through page allocates in any L1 data or L2 cache. Because it is not legal to map a physical page with multiple cacheability attributes, no Write-Through page can be brought into the cache from a different virtual address mapping. Therefore, memory requests for Write-Through cache lines are not looked-up in the cache. They are sent directly to the AXI master interface.


Normal Non-Cacheable memory is not looked-up in any cache. The requests are sent directly to memory. Read requests might over-read in memory, for example, reading 64 bytes of memory for a 4-byte access, and might satisfy multiple memory requests with a single external memory access. Write requests might be merged with other write requests to the same bytes or nearby bytes.

Strongly-ordered and Device

Strongly-ordered and Device memory types are used for communicating with input and output devices and memory-mapped peripherals. They are not looked-up in any cache.

For the Cortex-A15 processor, there is no distinction between shareable and nonshareable devices. Both Device and Strongly-ordered memory types are ordered together.

All the memory operations for a single instruction can be sent to the interconnect as a burst request. No Strongly-ordered or Device read request on the interconnect can cross an aligned 64-byte boundary. In addition, no Strongly-ordered or Device write request on the interconnect can cross an aligned 16-byte boundary.

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