10.4.1. Debug ID Register

The DBGDIDR characteristics are:

Purpose

Specifies:

  • the version of the Debug architecture that is implemented

  • some features of the debug implementation.

Usage constraints

There are no usage constraints. See the Debug Device ID Register 0 for more information about the debug implementation.

Configurations

Available in all configurations.

Attributes

See the register summary in Table 10.1.

Figure 10.2 shows the DBGDIDR bit assignments.

Figure 10.2. DBGDIDR bit assignments

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Table 10.2 shows the DBGDIDR bit assignments.

Table 10.2. DBGDIDR bit assignments

BitsNameFunction
[31:28]WRPs

The number of Watchpoint Register Pairs (WRPs) implemented. The number of implemented WRPs is one more than the value of this field.

0x3

The processor implements 4 WRPs.

[27:24]BRPs

The number of Breakpoint Register Pairs (BRPs) implemented. The number of implemented BRPs is one more than the value of this field.

0x5

The processor implements 6 BRPs.

[23:20]CTX_CMPs

The number of BRPs that can be used for Context matching. This is one more than the value of this field.

0x1

The processor implements two Context matching breakpoints, for example breakpoints 4 and 5.

[19:16]Version

The Debug architecture version.

0x5

The processor implements ARMv7, v7.1 Debug architecture.

[15]DEVID_imp

Debug Device ID Register bit.

1

DBGDEVID is implemented.

[14]nSUHD_imp

Secure User Halting Debug not implemented bit.

1

The processor does not implement Secure User Halting Debug.

[13]PCSR_imp

Program Counter Sampling Register (DBGPCSR) implemented as register 33 bit.

1

DBGPCSR is implemented as register 33.

[12]SE_imp

Security Extensions implemented bit.

1

The processor implements Security Extensions.

[11:8]-

Reserved.

[7:4]Variant

This field indicates the variant number of the processor. This number is incremented on functional changes. The value matches bits[23:20] of the CP15 Main ID Register. See Main ID Register for more information.

[3:0]Revision

This field indicates the revision number of the processor. This number is incremented on bug fixes. The value matches bits[3:0] of the CP15 Main ID Register. See Main ID Register for more information.


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