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10.4.13. Device Powerdown and Reset Control Register

The DBGPRCR characteristics are:

Purpose

Controls processor functionality related to reset and power down.

Usage constraints

There are no usage constraints.

Configurations

Required in all configurations.

Attributes

See the register summary in Table 10.1.

Figure 10.15 shows the DBGPRCR bit assignments.

Figure 10.15. DBGPRCR bit assignments

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Table 10.15 shows the DBGPRCR bit assignments.

Table 10.15. DBGPRCR bit assignments

BitsNameFunction
[31:4]-

Reserved, UNK/SBZP.

[3]COREPURQ

Core Power Up Request bit. This bit enables a debugger to request that the power controller powers up the core, enabling access to the debug registers in the core power domain:

0

DBGPWRUPREQ is LOW, this is the reset value.

1

DBGPWRUPREQ is HIGH. This bit is only defined for the memory-mapped and external debug interfaces. For accesses to DBGPRCR from CP14, this bit is UNK/SBZP.

This bit can be read and written when the core power domain is powered off, regardless of the value of DBGPRSR.DLK, OS Double Lock status bit. See the ARM Architecture Reference Manual for more information.

[2]HCWR

Hold Core Warm Reset bit. Writing 1 to this bit means the non-debug logic of the processor is held in reset after a core is powered up or a warm reset:

0

Does not hold the non-debug logic in reset on a power up or warm reset.

1

Holds the non-debug logic of the processor in reset on a power up or a warm reset. The processor is held in this state until this bit is cleared to 0.

For accesses to DBGPRCR from CP14, this bit is UNK/SBZP.

See the ARM Architecture Reference Manual for more information.

[1]CWRR

Core Warm Reset Request bit. Writing 1 to this bit issues a request for a warm reset:

0

No action.

1

Request internal reset using DBGRSTREQ output.

Reads from this bit are unknown, and writes to this bit from the memory-mapped or external debug interface are ignored when any of the following apply:

  • the core power domain is off

  • DBGPRSR.DLK, OS Double Lock status bit, is set to 1

  • for the external debug interface, the OS lock is set.

See the ARM Architecture Reference Manual for more information.

[0]CORENPDRQ

Core No Power down Request bit. When set to 1, the DBGNOPWRDWN output signal is HIGH. This output is connected to the system power controller and is interpreted as a request to operate in emulate mode. In this mode, the processor that includes PTM are not actually powered down when requested by software or hardware handshakes:

0

DBGNOPWRDWN is LOW. This is the reset value.

1

DBGNOPWRDWN is HIGH.

This bit is unknown on reads and ignores writes when any of the following apply:

  • The core power domain is powered down. If the CORENPDRQ bit is 1, it loses this value through the power down.

  • DBGPRSR.DLK, OS Double Lock status bit is set to 1.

  • For the external debug interface, the OS Lock is set.


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