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Home > Debug > Debug register descriptions > Device Powerdown and Reset Control Register |
The DBGPRCR characteristics are:
Controls processor functionality related to reset and power down.
There are no usage constraints.
Required in all configurations.
See the register summary in Table 10.1.
Figure 10.15 shows the DBGPRCR bit assignments.
Table 10.15 shows the DBGPRCR bit assignments.
Table 10.15. DBGPRCR bit assignments
Bits | Name | Function |
---|---|---|
[31:4] | - | Reserved, UNK/SBZP. |
[3] | COREPURQ | Core Power Up Request bit. This bit enables a debugger to request that the power controller powers up the core, enabling access to the debug registers in the core power domain:
This bit can be read and written when the core power domain is powered off, regardless of the value of DBGPRSR.DLK, OS Double Lock status bit. See the ARM Architecture Reference Manual for more information. |
[2] | HCWR | Hold Core Warm Reset bit. Writing 1 to this bit means the non-debug logic of the processor is held in reset after a core is powered up or a warm reset:
For accesses to DBGPRCR from CP14, this bit is UNK/SBZP. See the ARM Architecture Reference Manual for more information. |
[1] | CWRR | Core Warm Reset Request bit. Writing 1 to this bit issues a request for a warm reset:
Reads from this bit are unknown, and writes to this bit from the memory-mapped or external debug interface are ignored when any of the following apply:
See the ARM Architecture Reference Manual for more information. |
[0] | CORENPDRQ | Core No Power down Request bit. When set to 1, the DBGNOPWRDWN output signal is HIGH. This output is connected to the system power controller and is interpreted as a request to operate in emulate mode. In this mode, the processor that includes PTM are not actually powered down when requested by software or hardware handshakes:
This bit is unknown on reads and ignores writes when any of the following apply:
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