10.4.21. Peripheral Identification Registers

The Peripheral Identification Registers provide standard information required for all components that conform to the ARM Debug Interface v5 specification. They are a set of eight registers, listed in register number order in Table 10.23.

Table 10.23. Summary of the Peripheral Identification Registers

Peripheral ID40x040xFD0
Peripheral ID50x000xFD4
Peripheral ID60x000xFD8
Peripheral ID70x000xFDC
Peripheral ID00x0F0xFE0
Peripheral ID10xBC0xFE4
Peripheral ID2[a]0x2B0xFE8
Peripheral ID30x000xFEC

[a] Bits [7:4] of this value match the revision field in the Debug Identification Register, see Debug ID Register.

Only bits [7:0] of each Peripheral ID Register are used, with bits [31:8] reserved. Together, the eight Peripheral ID Registers define a single 64-bit Peripheral ID.

The ARM Architecture Reference Manual describes these registers.

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