10.4.8. Watchpoint Control Registers

The DBGWCR characteristics are:

Purpose

Holds control information for a watchpoint.

Usage constraints

Used in conjunction with a DBGWVR, see Watchpoint Value Registers. Each DBGWCR is associated with a DBGWVR to form a Watchpoint Register Pair (WRP). DBGWCRn is associated with DBGWVRn to form WRPn.

Configurations

The processor implements 4 WRPs, and is specified by the DBGDIDR.WRPs field, see Debug ID Register.

Attributes

See the register summary in Table 10.1. The debug logic reset value of a DBGWCR is UNK.

Figure 10.9 shows the DBGWCR bit assignments.

Figure 10.9. DBGWCR bit assignments

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Table 10.10 shows the DBGWCR bit assignments.

Table 10.10. DBGWCR bit assignments

BitsNameFunction
[31:29]-

Reserved.

[28:24]Mask

Address range mask. The processor supports watchpoint address range masking. This field can set a watchpoint on a range of addresses by masking lower order address bits out of the watchpoint comparison. The value of this field is the number of low order bits of the address that are masked off, except that values of 1 and 2 are reserved.

See the ARM Architecture Reference Manual for the meanings of watchpoint address range mask values.

[23:21]-

Reserved.

[20]WT

Watchpoint Type. This bit is set to 1 to link the watchpoint to a breakpoint to create a linked watchpoint that requires both data address matching and Context matching:

0

Unlinked data address match.

1

Linked data address match.

When this bit is set to 1 the linked BRP number field indicates the BRP to which this WRP is linked. See the ARM Architecture Reference Manual for more information.

[19:16]LBN

Linked Breakpoint Number. If this watchpoint is programmed with the watchpoint type set to linked, then this field must be programmed with the number of the breakpoint that defines the Context match to be combined with data address comparison. Otherwise, this field must be programmed to b0000.

Reading this register returns an unknown value for this field, and the generation of Watchpoint debug events is unpredictable, if either:

  • this watchpoint does not have linking enabled and this field is not programmed to b0000

  • this watchpoint has linking enabled and the breakpoint indicated by this field does not support Context matching, is not programmed for Context matching, or does not exist.

See the ARM Architecture Reference Manual for more information.

[15:14]SSC

Security State Control. This field enables the watchpoint to be conditional on the security state of the processor. This field is used with the Hyp Mode Control (HMC) and Privileged Access Control (PAC) fields.

See the ARM Architecture Reference Manual for possible values of the fields, and the access modes and security states that can be tested.

[13]HMC

Hyp Mode Control. This field is used with the Security State Control (SSC) and PAC fields. The value of DBGWCR.PAC has no effect for accesses made in Hyp mode.

See the ARM Architecture Reference Manual for possible values of the fields, and the access modes and security states that can be tested.

[12:5]BAS

Byte Address Select. The processor implements an 8-bit Byte address select field, DBGWCR[12:5].

A DBGWVR is programmed with a word-aligned address. This field enables the watchpoint to hit only if certain bytes of the addressed word are accessed. The watchpoint hits if an access hits any byte being watched, even if:

  • the access size is larger than the size of the region being watched

  • the access is unaligned, and the base address of the access is not in the same word of memory as the address in the DBGWVR

  • the access size is smaller than the size of region being watched.

See the ARM Architecture Reference Manual for more information.

[4:3]LSC

Load/store access control. This field enables watchpoint matching on the type of access being made:

b00

Reserved.

b01

Match on any load, Load-Exclusive, or swap.

b10

Match on any store, Store-Exclusive or swap.

b11

Match on all type of access.

[2:1]PAC

Privileged Access Control. This field enables watchpoint matching conditional on the mode of the processor. This field is used with the SSC and PAC fields.

See the ARM Architecture Reference Manual for possible values of the fields, and the access modes and security states that can be tested.

Note

  • For all cases the match refers to the privilege level of the access, not the mode of the processor. For example, if the watchpoint is configured to match only accesses at PL1 or higher, and the processor executes an LDRT instruction in a PL1 mode, the watchpoint does not match.

  • Permitted values of this field are not identical to those for the DBGBCR. In the DBGBCR the value b00 permitted.

[0]WE

Watchpoint Enable. This bit enables the watchpoint:

0

Watchpoint disabled.

1

Watchpoint enabled.

A watchpoint never generates a Watchpoint debug event when it is disabled.

For more information about possible watchpoint values, see Watchpoint Value Registers.

Note

The value of DBGWCR.E is unknown on reset. A debugger must ensure that DBGWCR.E has a defined value before it programs DBGDSCR[15:14] to enable debug.


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