10.4.14. Debug Self Address Offset Register

The DBGDSAR characteristics are:

Purpose

Defines the offset from the base address defined by DBGDRAR of the physical base address of the debug registers for the processor. See Debug ROM Address Register.

Usage constraints

This register is only visible in the CP14 interface, and therefore does not have a memory offset.

Configurations

The DBGDSAR is:

  • a 64-bit register when accessed by the MRRC instruction

  • a 32-bit register when accessed by the MRC instruction.

Attributes

See the register summary in Table 10.1.

Figure 10.16 shows the DBGDSAR bit assignments as a 32-bit register.

Figure 10.16. DBGDSAR 32-bit register bit assignments

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Figure 10.17. DBGDSAR 64-bit register bit assignments

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Table 10.16 shows the DBGDSAR bit assignments.

Table 10.16. DBGDSAR bit assignments

BitsNameFunction
[63:40]SGN

Sign extension. Each bit must be the same as DBGDSAR[39].

[39:32]SELFOFFSET[39:32]

Bits [39:32] of the two’s complement offset from the base address defined by DBGDRAR to the physical address where the debug registers are mapped. Bits [11:0] of the address are zero. See Debug ROM Address Register.

If DBGDSAR.Valid is zero, the value of this field is unknown.

[31:12]SELFOFFSET[31:12]

Bits [31:12] of the two’s complement offset from the base address defined by DBGDRAR to the physical address where the debug registers are mapped. Bits [11:0] of the address are zero. See Debug ROM Address Register.

If DBGDSAR.Valid is zero, the value of this field is unknown.

[11:2]-

Reserved.

[1:0]Valid

Valid bit. This field indicates whether the debug self address offset is valid:

b00

Offset is not valid.

b11

Offset is valid.


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