11.6. Events

Table 11.7 shows the events that are generated and the numbers that the PMU uses to reference the events. The table also shows the bit position of each event on the event bus. Event reference numbers that are not listed are reserved.

Table 11.7. PMU events

Event numberPMU event bus (to external)PMU event bus (to trace)Event name
0x00-[0]Instruction architecturally executed (condition check pass) - Software increment
0x01[0][1]Level 1 instruction cache refill
0x02[1][2]Level 1 instruction TLB refill
0x03[2][3]Level 1 data cache refill
0x04-[5:4]Level 1 data cache access
0x05-[7:6]Level 1 data TLB refill
0x08[6:3][11:8]Instruction architecturally executed
0x09[7][12]Exception taken
0x0A[8][13]Instruction architecturally executed (condition check pass) - Exception return
0x0B-[14]Instruction architecturally executed (condition check pass) - Write to CONTEXTIDR
0x10[9][15]Mispredicted or not predicted branch speculatively executed
0x12[10][17]Predictable branch speculatively executed
0x13-[19:18]Data memory access
0x14[11][20]Level 1 instruction cache access
0x15[12][21]Level 1 data cache Write-Back
0x16-[23:22]Level 2 data cache access
0x17[13][24]Level 2 data cache refill
0x18[14][25]Level 2 data cache Write-Back
0x19-[27:26]Bus access
0x1A-[28]Local memory error
0x1B-[30:29]Instruction speculatively executed
0x1C-[31]Instruction architecturally executed (condition check pass) - Write to translation table base
0x1D-[32]Bus cycle
0x40[15][33]Level 1 data cache access - Read
0x41[16][34]Level 1 data cache access - Write
0x42-[35]Level 1 data cache refill - Read
0x43-[36]Level 1 data cache refill - Write
0x46-[37]Level 1 data cache Write-Back - Victim
0x47-[38]Level 1 data cache Write-Back - Cleaning and coherency
0x48-[39]Level 1 data cache invalidate
0x4C[17][40]Level 1 data TLB refill - Read
0x4D[18][41]Level 1 data TLB refill - Write
0x50[19][42]Level 2 data cache access - Read
0x51[20][43]Level 2 data cache access - Write
0x52-[44]Level 2 data cache refill - Read
0x53-[45]Level 2 data cache refill - Write
0x56-[46]Level 2 data cache Write-Back - Victim
0x57-[47]Level 2 data cache Write-Back - Cleaning and coherency
0x58-[48]Level 2 data cache invalidate
0x60-[49]Bus access - Read
0x61-[50]Bus access - Write
0x62-[52:51]Bus access - Normal
0x63-[54:53]Bus access - Not normal
0x64-[56:55]Bus access - Normal
0x65-[58:57]Bus access - Peripheral
0x66-[59]Data memory access - Read
0x67-[60]Data memory access - Write
0x68-[61]Unaligned access - Read
0x69-[62]Unaligned access - Write
0x6A-[64:63]Unaligned access
0x6C[21][65]Exclusive instruction speculatively executed - LDREX
0x6D[22][66]Exclusive instruction speculatively executed - STREX pass
0x6E[23][67]Exclusive instruction speculatively executed - STREX fail
0x70-[69:68]Instruction speculatively executed - Load
0x71-[71:70]Instruction speculatively executed - Store
0x72-[73:72]Instruction speculatively executed - Load or store
0x73-[75:74]Instruction speculatively executed - Integer data processing
0x74-[77:76]Instruction speculatively executed - Advanced SIMD
0x75-[79:78]Instruction speculatively executed - VFP
0x76-[81:80]Instruction speculatively executed - Software change of the PC
0x78-[82]Branch speculatively executed - Immediate branch
0x79-[83]Branch speculatively executed - Procedure return
0x7A-[84]Branch speculatively executed - Indirect branch
0x7C-[85]Barrier speculatively executed - ISB
0x7D[24][86]Barrier speculatively executed - DSB
0x7E[24][87]Barrier speculatively executed - DMB

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