11.4.1. Performance Monitor Configuration Register

The PMCFGR characteristics are:

Purpose

Contains PMU-specific configuration data.

Usage constraints

There are no usage constraints.

Configurations

Available in all configurations.

Attributes

See the register summary in Table 11.1.

Figure 11.2 shows the PMCFGR bit assignments.

Figure 11.2. PMCFGR bit assignments

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Table 11.2 shows the PMCFGR bit assignments.

Table 11.2. PMCFGR bit assignments

BitsNameFunction
[31:20]-

Reserved.

[19]UEN

User mode enable register supported bit:

1

User mode enable register supported. PMUSERENR is a writable register.

[18]WT

Control state machine:

0

The control state machine is not implemented. PMCR.WT reads as zero.

[17]NA

No access to counters when running:

0

The counters can generally be read at any time. However, the PMCR.NA bit might still indicate no access from time to time.

Reads of the counters in this state return unknown, and writes to the counters and per-counter controls are Unpredictable.

[16]EX

Export supported:

1

Export is supported. PMCR.EX is writable.

[15]CCD

Cycle counter has pre-scale:

1

The cycle counter counts every 64th cycle. PMCR.CCD is writable.

[14]CC

Dedicated cycle counter supported:

1

Dedicated cycle counter is supported.

[13]-

Reserved.

[12:11]Size

Counter size:

b11

32-bit counters.

[10:8]-

Reserved.

[7:0]N

Number of event counters:

b00000110

Six counters.


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