11.4.2. Performance Monitor Control Register

The PMCR characteristics are:

Purpose

Provides information on the Performance Monitors implementation, including the number of counters implemented, and configures and controls the counters.

Usage constraints

The PMCR is:

  • a read/write register

  • Common to the Secure and Non-secure states

  • accessible in Hyp mode, and all modes executing at PL1 when HDCR.TPM and HDCR.TPMCR are set to 0

  • accessible in User mode only when PMUSERENR.EN is set to 1, HDCR.TPM and HDCR.TPMCR are set to 0.

Configurations

Available in all configurations.

Attributes

See the register summary in Table 11.1.

Figure 11.3 shows the PMCR bit assignments.

Figure 11.3. PMCR bit assignments

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Table 11.3 shows the PMCR bit assignments.

Table 11.3. PMCR bit assignments

BitsNameFunction
[31:24]IMP

Implementer code:

0x41

ARM.

This is a read-only field.

[23:16]IDCODE

Identification code:

0x0F

Cortex-A15.

This is a read-only field.

[15:11]N

Number of event counters.

In Non-secure modes other than Hyp mode, this field reads the value of HDCR.HPMN. See Hyp Debug Configuration Register.

In Secure state and Hyp mode, this field returns 0x6 that indicates the number of counters implemented.

This is a read-only field.

[10:6]-

Reserved, UNK/SBZP.

[5]DP

Disable cycle counter, PMCCNTR when prohibited:

0

Count is enabled in prohibited regions. This is the reset value.

1

Count is disabled in prohibited regions.

This bit is read/write. For more information on prohibited regions, see the ARM Architecture Reference Manual.

[4]X

Export enable. This bit permits events to be exported to another debug device, such as a trace macrocell, over an event bus:

0

Export of events is disabled. This is the reset value.

1

Export of events is enabled.

This bit is read/write and does not affect the generation of Performance Monitors interrupts, that can be implemented as a signal exported from the processor to an interrupt controller.

[3]D

Clock divider:

0

When enabled, PMCCNTR counts every clock cycle. This is the reset value.

1

When enabled, PMCCNTR counts every 64 clock cycles.

This bit is read/write.

[2]C

Clock counter reset:

0

No action.

1

Reset PMCCNTR to 0.

Note

Resetting PMCCNTR does not clear the PMCCNTR overflow bit to 0. See the ARM Architecture Reference Manual for more information.

This bit is write-only, and always RAZ.

[1]P

Event counter reset:

0

No action.

1

Reset all event counters, not including PMCCNTR, to 0.

In Non-secure modes other than Hyp mode, a write of 1 to this bit does not reset event counters that the HDCR.HPMN field reserves for Hyp mode use. See Hyp Debug Configuration Register.

In Secure state and Hyp mode, a write of 1 to this bit resets all the event counters.

[0]E

Enable bit. This bit does not disable or enable, counting by event counters reserved for Hyp mode by HDCR.HPMN. It also does not suppress the generation of performance monitor overflow interrupt requests by those counters:

0

All counters, including PMCCNTR, are disabled. This is the reset value.

1

All counters are enabled.

This bit is read/write.


To access the PMCR, read or write the CP15 registers with:

MRC p15, 0, <Rt>, c9, c12, 0; Read Performance Monitor Control Register
MCR p15, 0, <Rt>, c9, c12, 0; Write Performance Monitor Control Register
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