5.2.2. L1 data TLB

There are two separate 32-entry fully-associative TLBs that are used for data loads and stores, respectively. Similar to the L1 instruction TLB, both of these cache entries at the 4KB granularity of VA to PA mappings only.

A hit in the data load or store TLBs provides a single CLK cycle access to the translation, and returns the physical address to the instruction cache for comparison. It also checks the access permissions to signal a Data Abort.

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