14.2.2. Enabling Advanced SIMD and VFP extensions

From reset, both the Advanced SIMD and VFP extensions are disabled. Any attempt to execute either an Advanced SIMD or VFP instruction results in an Undefined Instruction exception being taken. To enable software access to the Advanced SIMD and VFP features, ensure that:

To enable Advanced SIMD and VFP operations, software must set the FPEXC.EN bit to 1. See Floating-Point Exception Register.

When Advanced SIMD and VFP operation is disabled because FPEXC.EN is 0, all Advanced SIMD and VFP instructions are treated as undefined except for execution of the following in privileged modes:

See the ARM Architecture Reference Manual for more information on enabling Advanced SIMD and VFP support.

Using the Advanced SIMD and VFP in Secure state only

To use the Advanced SIMD and VFP in Secure state only, you must first program the CPACR and FPEXC registers. See Coprocessor Access Control Register and Floating-Point Exception Register.

  1. Enable access to CP10 and CP11 and clear the ASEDIS bit in the CPACR:

    MOV r0, 0x00F00000
    
    MCR p15, 0, r0, c1, c0, 2
    
    ISB
    
  2. Set the FPEXC.EN bit to enable Advanced SIMD and VFP:

    MOV r3, #0x40000000
    
    VMSR FPEXC, r3
    

Using the Advanced SIMD and VFP in Secure state and Non-secure state other than Hyp mode

To use the Advanced SIMD and VFP in Secure state and Non-secure state other than Hyp mode, you must first define the NSACR, then define the CPACR and FPEXC registers. See Non-Secure Access Control Register, Coprocessor Access Control Register, and Floating-Point Exception Register.

  1. Enable Non-secure access to CP10 and CP11 and clear the NSASEDIS bit in the NSACR:

    MRC p15, 0, r0, c1, c1, 2
    
    ORR r0, r0, #(3<<10)	    ; Enable Non-secure access to CP10 and CP11
    
    BIC r0, r0, #(3<<14)	    ; Clear NSASEDIS bit
    
    MCR p15, 0, r0, c1, c1, 2
    
    ISB
    
  2. Enable access to CP10 and CP11 and clear the ASEDIS bit in the CPACR:

    MOV r0, 0x00F00000
    
    MCR p15, 0, r0, c1, c0, 2
    
    ISB
    
  3. Set the FPEXC.EN bit to enable Advanced SIMD and VFP:

    MOV r3, #0x40000000
    
    VMSR FPEXC, r3
    

Using the Advanced SIMD and VFP in Hyp mode

To use the Advanced SIMD and VFP in Hyp mode, you must first define the NSACR, then define the HCPTR and FPEXC registers.

  1. Enable Non-secure access to CP10 and CP11 and clear the NSASEDIS bit in the NSACR:

    MRC p15, 0, r0, c1, c1, 2
    
    ORR r0, r0, #(3<<10)	;    Enable Non-secure access to CP10 and CP11
    
    BIC r0, r0, #(3<<14);    Clear the NSASEDIS bit
    
    MCR p15, 0, r0, c1, c1, 2
    
    ISB
    
  2. Clear the TCP10, TCP11, and TASE bits in the HCPTR:

    MRC p15, 4, r0, c1, c1, 2
    
    BIC r0, r0, #(3<<10);    Clear the TCP10 and TCP11 bits
    
    BIC r0, r0, #(3<<14);    Clear the TASE bit
    
    MCR p15, 4, r0, c1, c1, 2
    
    ISB
    
  3. Set the FPEXC.EN bit to enable Advanced SIMD and VFP:

    MOV r3, #0x40000000
    
    VMSR FPEXC, r3
    

At this point the processor can execute Advanced SIMD and VFP instructions.

Note

Operation is Unpredictable if you configure the Coprocessor Access Control Register (CPACR) such that CP10 and CP11 do not have identical access permissions.

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