Cortex-A15 Technical Reference Manual: 4.2.3. c2 registers

Table 4.4 shows the 32-bit wide CP15 system control registers when CRn is c2.

Table 4.4. c2 register summary

Op1	CRm	Op2	Name	Reset	Description
0	c0	0	TTBR0	UNK	Translation Table Base Register 0 and Register 1
		1	TTBR1	UNK	Translation Table Base Register 0 and Register 1
		2	TTBCR	`0x00000000`^[a]	Translation Table Base Control Register
4	c0	2	HTCR	UNK	Hyp Translation Control Register
	c1	2	VTCR	UNK	Virtualization Translation Control Register, see the ARM Architecture Reference Manual
^[a]The reset value is `0x00000000` for the Secure copy of the register. The reset value for the EAE bit of the Non-Secure copy of the register is `0x0`. You must program the Non-Secure copy of the register with the required initial value, as part of the processor boot sequence.

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