Cortex-A15 Technical Reference Manual: 12.6. Register summary

12.6. Register summary

This section summarizes the PTM registers. For full descriptions of the PTM registers, see:

Register descriptions, for the implementation-defined registers
the CoreSight Program Flow Trace Architecture Specification, for the other registers.

Note

Registers not listed here are not implemented. Reading a non-implemented register address returns 0. Writing to a non-implemented register address has no effect.
In Table 12.4, access type is described as follows:
RW
Read and write.
RO
Read only.
WO
Write only.

All PTM registers are 32 bits wide. The PTM registers are defined in the CoreSight Program Flow Trace Architecture Specification. Table 12.4 lists all of the registers that are implemented in the PTM with their offsets from a base address. This base address is defined by the system integrator when placing the PTM in the Debug-APB memory map.

Table 12.4. PTM register summary

Base offset		Function	Type	Description
PTM configuration
	`0x000`	Main Control	RW	Main Control Register
	`0x004`	Configuration Code	RO	Configuration Code Register
	`0x008`	Trigger Event	RW	CoreSight Program Flow Trace Architecture Specification
	`0x010`	Status	RW	CoreSight Program Flow Trace Architecture Specification
	`0x014`	System Configuration	RO	System Configuration Register
TraceEnable control
	`0x018`	TraceEnable Start/Stop Control	RW	TraceEnable Start/Stop Control Register
	`0x020`	TraceEnable Event	RW	CoreSight Program Flow Trace Architecture Specification
	`0x024`	TraceEnable Control	RW	TraceEnable Control Register 1
Address comparators
	`0x040`-`0x05C`	Address Comparator Value 1- 8	RW	CoreSight Program Flow Trace Architecture Specification
	`0x080`-`0x09C`	Address Comparator Access Type 1- 8	RW	CoreSight Program Flow Trace Architecture Specification
Counters
	`0x140`-`0x144`	Counter Reload Value 1-2	RW	CoreSight Program Flow Trace Architecture Specification
	`0x150`-`0x154`	Counter Enable 1-2	RW
	`0x160`-`0x164`	Counter Reload Event 1-2	RW
	`0x170`-`0x174`	Counter Value 1-2	RW
Sequencer registers
	`0x180`-`0x194`	Sequencer State Transition Event 1-6	RW	CoreSight Program Flow Trace Architecture Specification
	`0x19C`	Current Sequencer State	RW	CoreSight Program Flow Trace Architecture Specification
External output event
	`0x1A0`-`0x1A4`	External Output Event 1-2	RW	CoreSight Program Flow Trace Architecture Specification
Context ID comparators
	`0x1B0`	Context ID Comparator Value 1	RW	CoreSight Program Flow Trace Architecture Specification
	`0x1BC`	Context ID Comparator Mask	RW	CoreSight Program Flow Trace Architecture Specification
General control
	`0x1E0`	Synchronization Frequency	RW	Synchronization Frequency Register
	`0x1E4`	ID	RO	See ETM ID Register
	`0x1E8`	Configuration Code Extension	RO	Configuration Code Extension Register
	`0x1EC`	Extended External Input Selection	RW	Extended External Input Selection Register
	`0x1F8`	Timestamp Event	RW	CoreSight Program Flow Trace Architecture Specification
	`0x1FC`	Auxiliary Control Register	RW	Auxiliary Control Register
	`0x200`	CoreSight Trace ID	RW	CoreSight Program Flow Trace Architecture Specification
	`0x204`	VMID Comparator value	RW	CoreSight Program Flow Trace Architecture Specification
	`0x300`	OS Lock Access Specification	WO	CoreSight Program Flow Trace Architecture Specification
	`0x304`	OS Lock Status	RO	CoreSight Program Flow Trace Architecture Specification
	`0x310`	Power Down Control	RW	Power Down Control Register
	`0x314`	Power Down Status	RO	CoreSight Program Flow Trace Architecture Specification
Integration registers
	`0xEDC`	Miscellaneous Outputs	WO	Miscellaneous Output Register
	`0xEE0`	Miscellaneous Inputs	RO	Miscellaneous Input Register
	`0xEE8`	Trigger	WO	Trigger Register
	`0xEEC`	ATB Data 0	WO	Figure 12.15
	`0xEF0`	ATB Control 2	RO	ATB Control Register 2
	`0xEF4`	ATB Identification	WO	ATB Identification Register
	`0xEF8`	ATB Control 0	WO	ATB Control Register 0
	`0xF00`	Integration Mode Control	RW	Integration Mode Control Register
	`0xFA0`	Claim Tag Set	RW	CoreSight Program Flow Trace Architecture Specification
	`0xFA4`	Claim Tag Clear	RW	CoreSight Program Flow Trace Architecture Specification
	`0xFB0`	Lock Access	WO	CoreSight Program Flow Trace Architecture Specification
	`0xFB4`	Lock Status	RO	CoreSight Program Flow Trace Architecture Specification
	`0xFB8`	Authentication Status	RO	CoreSight Program Flow Trace Architecture Specification
	`0xFC8`	Device Configuration	RO	CoreSight Program Flow Trace Architecture Specification
	`0xFCC`	Device Type	RO	CoreSight Program Flow Trace Architecture Specification
Peripheral and Component ID registers
	`0xFD0`	Peripheral ID4	RO	Peripheral Identification Registers
	`0xFD4`	Peripheral ID5	RO
	`0xFD8`	Peripheral ID6	RO
	`0xFDC`	Peripheral ID7	RO
	`0xFE0`	Peripheral ID0	RO
	`0xFE4`	Peripheral ID1	RO
	`0xFE8`	Peripheral ID2	RO
	`0xFEC`	Peripheral ID3	RO
	`0xFF0`	Component ID0	RO	Component Identification Registers
	`0xFF4`	Component ID1	RO
	`0xFF8`	Component ID2	RO
	`0xFFC`	Component ID3	RO

For more information about these registers and the packets implemented by the PTM, see the CoreSight Program Flow Trace Architecture Specification.

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Non-Confidential	ID122011
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