12.7.20. Peripheral Identification Registers

The Peripheral Identification Registers provide standard information required for all CoreSight components. They are a set of eight registers, listed in register number order in Table 12.22.

Table 12.22. Summary of the Peripheral ID Registers

RegisterValueOffset
Peripheral ID40x040xFD0
Peripheral ID50x000xFD4
Peripheral ID60x000xFD8
Peripheral ID70x000xFDC
Peripheral ID00x5F0xFE0
Peripheral ID10xB90xFE4
Peripheral ID2[a]0x2B0xFE8
Peripheral ID30x000xFEC

[a] Bits [7:4] of this value match the revision field in the ID Register, see ETM ID Register.


Only bits [7:0] of each Peripheral ID Register are used, with bits [31:8] reserved. Together, the eight Peripheral ID Registers define a single 64-bit Peripheral ID.

The CoreSight Program Trace Flow Architecture Specification describes these registers.

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