12.5.5. Interaction with the performance monitoring unit

The processor includes a Performance Monitoring Unit (PMU) that enables events, such as cache misses and instructions executed, to be counted over a period of time. This section describes how the PMU and PTM function together.

Use of PMU events by the PTM

All PMU architectural events are available to the PTM through the extended input facility. See the ARM Architectural Reference Manual for more information on PMU events.

The PTM uses two extended external input selectors to access the PMU events. Each selector can independently select one of the PMU events, which are then active for the cycles where the relevant events occur. These selected events can then be accessed by any of the event registers within the PTM.

Effect of debug double lock on trace register access

All trace register accesses through the memory-mapped and external debug interfaces behave as if the processor power domain is off when debug double lock is set. For more information on debug double lock, see the ARM Architecture Reference Manual.

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