4.2.2. c1 registers

Table 4.3 shows the 32-bit wide CP15 system control registers when CRn is c1.

Table 4.3. c1 register summary

Op1CRmOp2NameResetDescription
0c00SCTLR0x00C50078[a]

System Control Register

  1ACTLR

0x00000000

Auxiliary Control Register

  2CPACR0x00000000[b]

Coprocessor Access Control Register

 c10SCR0x00000000

Secure Configuration Register

  1SDERUNKSecure Debug Enable Register, see the ARM Architecture Reference Manual
  2NSACR

0x00000000[c]

Non-Secure Access Control Register

4c00HSCTLRUNK

Hyp System Control Register

  1HACTLRUNK

Hyp Auxiliary Control Register

 c10HCR0x00000000

Hyp Configuration Register, see the ARM Architecture Reference Manual

  1HDCR0x00000006[d]

Hyp Debug Configuration Register

  2HCPTR0x000033FF[e]

Hyp Coprocessor Trap Register

  3HSTR0x00000000

Hyp System Trap Register, see the ARM Architecture Reference Manual

  7HACRUNK

Hyp Auxiliary Configuration Register

[a] The reset value depends on primary inputs, CFGTE, CFGEND, and VINITHI. The value shown in Table 4.3 assumes these signals are set to zero.

[b] The reset value depends on the VFP and NEON configuration. If VFP and NEON are implemented, the reset value is 0x00000000. If VFP is implemented but NEON is not implemented, the reset value is 0x80000000. If VFP and NEON are not implemented, the reset value is 0x00000000.

[c] The reset value depends on the VFP and NEON configuration. If VFP and NEON are implemented, the reset value is 0x00000000. If VFP is implemented but NEON is not implemented, the reset value is 0x00008000. If VFP and NEON are not implemented, the reset value is 0x00000000.

[d] The reset value for bit [7] is UNK.

[e] The reset value depends on the VFP and NEON configuration. If VFP and NEON are implemented, the reset value is 0x000033FF. If VFP is implemented but NEON is not implemented, the reset value is 0x0000B3FF. If VFP and NEON are not implemented, the reset value is 0x0000BFFF.


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