3.5.2. Security Extensions configuration write access disable

The processor pin CP15SDISABLE disables write access to certain registers in the CP15 System Control Coprocessor. There is one CP15SDISABLE input for each processor. Attempts to write to these registers when CP15SDISABLE is HIGH result in an Undefined Instruction exception. Reads from the registers are still permitted.

You can use the CP15SDISABLE pin to disable subsequent write access to the system control processor registers after the Secure boot code runs. This protects the configuration set up by the Secure boot code.

A change to the CP15SDISABLE pin takes effect on the instructions decoded by the processor as quickly as possible. Software must perform an ISB instruction after a change to this pin on the boundary of the macrocell has occurred, to ensure that its effect is recognized for following instructions. It it is expected that:

See Registers affected by CP15SDISABLE for a list of the system registers affected by CP15SDISABLE.

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