12.5.3. Event definitions

As described in the CoreSight Program Trace Flow Architecture Specification, there are several event registers that you can program to select specific inputs as control events. Table 12.3 shows the event resources defined for the PTM.

Table 12.3. Event resource definitions

Resource typeIndex valuesDescription
b0000-7

Single address comparator 1-8

b0010-3

Address range comparator 1-4

b1000-1

Counter 1-2 at zero

b1010-2

Sequencer in states 1-3

8

Context ID comparator

11

VMID comparator

15

Trace start/stop resource

b1100-3

External inputs 1-4

8-9

Extended external input selectors 1-2

13

Processor is in Non-secure state

14

Trace prohibited by processor

15

Hard-wired resource (always true)


Copyright © 2011 ARM. All rights reserved.ARM DDI 0438D
Non-ConfidentialID122011