4.2.15. 64-bit registers

Table 4.15 gives a summary of the 64-bit wide CP15 system control registers, accessed by the MCCR and MRRC instructions.

Table 4.15. 64-bit register summary

CRnOp1CRmOp2NameResetDescription
-0c2-TTBR0UNK

Translation Table Base Register 0, see the ARM Architecture Reference Manual

-1c2-TTBR1UNK

Translation Table Base Register 1, see the ARM Architecture Reference Manual

-4c2-HTTBRUNK

Hyp Translation Table Base Register, see the ARM Architecture Reference Manual

-6c2-VTTBRUNK[a]

Virtualization Translation Table Base Register, see the ARM Architecture Reference Manual

-0c7-PARUNK

Physical Address Register

-0c14-CNTPCTUNK

Physical Count Register, see the ARM Architecture Reference Manual

-1c14-CNTVCTUNK

Virtual Count Register, see the ARM Architecture Reference Manual

-2c14-CNTP_CVALUNK

PL1 Physical Timer CompareValue Register, see the ARM Architecture Reference Manual

-3c14-CNTV_CVALUNK

Virtual Timer CompareValue Register, see the ARM Architecture Reference Manual

-4c14-CNTVOFFUNK

Virtual Offset Register, see the ARM Architecture Reference Manual

-6c14-CNTHP_CVALUNK

PL2 Physical Timer CompareValue Register, see the ARM Architecture Reference Manual

-0c15-CPUMERRSR-[b]CPU Memory Error Syndrome Register
-1c15-L2MERRSR-[b]L2 Memory Error Syndrome Register

[a] The reset value for bits [55:48] is b00000000.

[b] The reset value for bits [63,47:40,39:32,31] are all b0.


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