12.5.1. Modes of operation

When the PTM is powered on or reset, you must program all PTM registers before you enable tracing. If you do not do so, the trace results are unpredictable.

When programming the PTM registers you must enable all the changes at the same time. For example, if the counter is reprogrammed before the trigger condition has been correctly set up, it might start to count based on incorrect events.

You access the PTM registers through the CoreSight Debug APB bus. The PTM implements the CoreSight lock access mechanism, and can distinguish between memory-mapped accesses from on-chip software and memory-mapped accesses from a debugger, for example by using the CoreSight Debug Access Port (DAP).

See the CoreSight Program Flow Trace Architecture Specification for more information about programming the PTM.

The following sections describe how you control PTM programming:

Using the Programming bit

Use the Programming bit in the Main Control Register, see Main Control Register, to disable all operations during programming.

When the Programming bit is set to 0 you must not write to registers other than the Main Control Register, because this can lead to unpredictable behavior.

When setting the Programming bit, you must not change any other bits of the Main Control Register. You must only change the value of bits other than the Programming bit of the Control Register when bit [1] of the Status Register is set to 1. ARM recommends that you use a read-modify-write procedure when changing the Main Control Register. For information on the Status Register, see the CoreSight Program Flow Trace Architecture Specification.

When the Programming bit is set to 1:

  • the FIFO is permitted to empty and no more trace is produced

  • the counters, sequencer, and start/stop block are held in their current state

  • the external outputs are forced LOW.

Programming registers

You program and read the PTM registers using the debug APB interface. A reset of the PTM initializes the following registers:

To start tracing, you must program the following registers to avoid unpredictable behavior:

You might also require to program the following:

  • Address Comparator Registers if the respective address comparators are used

  • Counter Registers if the respective counters are used

  • Sequencer Registers if the sequencer is used

  • External Output Event Registers if the external outputs are used

  • Context ID Comparator Registers if the context ID comparator is used

  • VM ID Comparator Register if the VM ID comparator is used

  • Timestamp Event Register is timestamping is used

  • Extended External Input Selection Register if the extended external inputs are used.

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