Cortex-A15 Technical Reference Manual: 4.2.21. TLB maintenance operations

Table 4.21 shows the 32-bit wide TLB maintenance operations.

Table 4.21. TLB maintenance operations

Name	CRn	Op1	CRm	Op2	Reset	Description
TLBIALLIS	c8	0	c3	0	UNK	Invalidate entire unified TLB Inner Shareable, see the ARM Architecture Reference Manual
TLBIMVAIS				1	UNK	Invalidate unified TLB by MVA and ASID Inner Shareable, see the ARM Architecture Reference Manual
TLBIASIDIS				2	UNK	Invalidate unified TLB by ASID Inner Shareable, see the ARM Architecture Reference Manual
TLBIMVAAIS				3	UNK	Invalidate unified TLB by MVA all ASID Inner Shareable, see the ARM Architecture Reference Manual
ITLBIALL			c5	0	UNK	Invalidate entire instruction TLB, see the ARM Architecture Reference Manual
ITLBIMVA				1	UNK	Invalidate instruction TLB entry by MVA and ASID, see the ARM Architecture Reference Manual
ITLBIASID				2	UNK	Invalidate instruction TLB by ASID, see the ARM Architecture Reference Manual
DTLBIALL			c6	0	UNK	Invalidate entire data TLB, see the ARM Architecture Reference Manual
DTLBIMVA				1	UNK	Invalidate data TLB entry by MVA and ASID, see the ARM Architecture Reference Manual
DTLBIASID				2	UNK	Invalidate data TLB by ASID, see the ARM Architecture Reference Manual
TLBIALL			c7	0	UNK	Invalidate entire unified TLB, see the ARM Architecture Reference Manual
TLBIMVA				1	UNK	Invalidate unified TLB by MVA and ASID, see the ARM Architecture Reference Manual
TLBIASID				2	UNK	Invalidate unified TLB by ASID, see the ARM Architecture Reference Manual
TLBIMVAA				3	UNK	Invalidate unified TLB by MVA all ASID, see the ARM Architecture Reference Manual

The Virtualization Extensions include additional TLB operations for use in Hyp mode. For more information, see Hyp mode TLB maintenance operations.

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