Cortex-A15 Technical Reference ManualRevision: r2p1
Home > System Control > Register summary > Identification registers

4.2.16. Identification registers

Table 4.16 shows the 32-bit wide Identification registers.

Table 4.16. Identification registers

NameCRnOp1CRmOp2ResetDescription
MIDRc00c000x412FC0F1

Main ID Register

CTR   10x8444C004[a]

Cache Type Register

TCMTR   20x00000000

TCM Type Register

TLBTR   30x00000000

TLB Type Register

MPIDR   5-[b]

Multiprocessor Affinity Register

REVIDR   60x00000000

Revision ID Register

MIDR   4, 70x412FC0F1

Aliases of Main ID Register, Main ID Register

ID_PFR0  c100x00001131

Processor Feature Register 0

ID_PFR1   10x00011011

Processor Feature Register 1

ID_DFR0   20x02010555

Debug Feature Register 0

ID_AFR0   30x00000000Auxiliary Feature Register 0
ID_MMFR0   40x10201105

Memory Model Feature Register 0

ID_MMFR1   50x20000000

Memory Model Feature Register 1

ID_MMFR2   60x01240000

Memory Model Feature Register 2

ID_MMFR3   70x02102211

Memory Model Feature Register 3

ID_ISAR0  c200x02101110

Instruction Set Attribute Register 0

ID_ISAR1   10x13112111

Instruction Set Attribute Register 1

ID_ISAR2   20x21232041

Instruction Set Attribute Register 2

ID_ISAR3   30x11112131

Instruction Set Attribute Register 3

ID_ISAR4   40x10011142

Instruction Set Attribute Register 4

ID_ISAR5   50x00000000

Instruction Set Attribute Register 5

CCSIDR 1c00UNK

Cache Size ID Register

CLIDR   10x0A200023

Cache Level ID Register

AIDR   70x00000000

Auxiliary ID Register

CSSELR 2c00UNKCache Size Selection Register

[a] The reset value depends on the primary input, IMINLN. The value shown in Table 4.16 assumes IMINLN is set to 1.

[b] The reset value depends on the primary input, CLUSTERID, and the number of configured processors in the MPCore device.


Copyright © 2011 ARM. All rights reserved.ARM DDI 0438D
Non-ConfidentialID122011
PDF file icon  PDF version
Home > System Control > Register summary > Identification registers