4.2.25. Security Extensions registers

Table 4.25 shows the 32-bit wide Security Extensions registers.

Table 4.25. Security Extensions registers

NameCRnOp1CRmOp2ResetDescription
SCRc10c100x00000000

Secure Configuration Register

SDER   1UNKSecure Debug Enable Register, see the ARM Architecture Reference Manual
NSACR   2

0x00000000[a]

Non-Secure Access Control Register

VBARc120c00

0x00000000[b]

Vector Base Address Register, see the ARM Architecture Reference Manual

MVBAR   1UNK

Monitor Vector Base Address Register, see the ARM Architecture Reference Manual

ISR  c10UNK

Interrupt Status Register, see the ARM Architecture Reference Manual

[a] The reset value depends on the VFP and NEON configuration. If VFP and NEON are implemented, the reset value is 0x00000000. If VFP is implemented but NEON is not implemented, the reset value is 0x00008000. If VFP and NEON are not implemented, the reset value is 0x00000000.

[b] The reset value is 0x00000000 for the Secure copy of the register. You must program the Non-secure copy of the register with the required initial value, as part of the processor boot sequence.


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