4.2.29. Implementation defined registers

Table 4.28 shows the implementation defined registers. These registers provide test features and any required configuration options specific to the Cortex-A15 processor.

Table 4.28. Implementation defined registers




Auxiliary Control Register


L2 Control Register

L2ECTLR   30x0000000032-bit

L2 Extended Control Register


Instruction L1 Data n Register

IL1DATA1   1UNK32-bit

Instruction L1 Data n Register

IL1DATA2   2UNK32-bit

Instruction L1 Data n Register

DL1DATA0  c10UNK32-bit

Data L1 Data n Register

DL1DATA1   1UNK32-bitData L1 Data n Register
DL1DATA2   2UNK32-bit

Data L1 Data n Register

DL1DATA3   3UNK32-bitData L1 Data n Register
RAMINDEX  c40UNK32-bit

RAM Index Register

L2ACTLR 1c000x0000000032-bit

L2 Auxiliary Control Register

L2PFR   30x000009B032-bit

L2 Prefetch Control Register

CBAR 4c00-[b]32-bit

Configuration Base Address Register

CPUMERRSR-0c15--[c]64-bitCPU Memory Error Syndrome Register
L2MERRSR-1c15--[c]64-bitL2 Memory Error Syndrome Register

[a] The reset value depends on the processor configuration.

[b] The reset value depends on the primary input, PERIPHBASE[39:15].

[c] The reset value for bits [63,47:40,39:32,31] are all zero.

Copyright © 2011 ARM. All rights reserved.ARM DDI 0438D