2.4.1. Dynamic power management

This section describes the following dynamic power management features in the Cortex-A15 processor:

Processor Wait for Interrupt

Wait for Interrupt is a feature of the ARMv7-A architecture that puts the processor in a low power state by disabling most of the clocks in the processor while keeping the processor powered up. This reduces the power drawn to the static leakage current, leaving a small clock power overhead to enable the processor to wake up from WFI mode.

A processor enters into WFI mode by executing the WFI instruction.

When executing the WFI instruction, the processor waits for all instructions in the processor to retire before entering the idle or low power state. The WFI instruction ensures that all explicit memory accesses occurred before the WFI instruction in program order, have retired. For example, the WFI instruction ensures that the following instructions received the required data or responses from the L2 memory system:

  • load instructions

  • cache and TLB maintenance operations

  • store exclusives instructions.

In addition, the WFI instruction ensures that store instructions have updated the cache or have been issued to the L2 memory system.

While the processor is in WFI mode, the clocks in the processor are temporarily enabled without causing the processor to exit WFI mode, when any of the following events are detected:

  • an L2 snoop request that must be serviced by the processor L1 data cache

  • a cache, TLB or BTB maintenance operation that must be serviced by the processor L1 instruction cache, data cache, instruction TLB, data TLB, or BTB

  • an APB access to the debug or trace registers residing in the processor power domain.

Exit from WFI mode occurs when the processor detects a reset or one of the WFI wake up events as described in the ARM Architecture Reference Manual.

On entry into WFI mode, STANDBYWFI for that processor is asserted. Assertion of STANDBYWFI guarantees that the processor is in idle and low power state. STANDBYWFI continues to assert even if the clocks in the processor are temporarily enabled because of an L2 snoop request, cache, TLB, and BTB maintenance operation or an APB access.

Figure 2.12 shows the upper bound for the STANDBYWFI deassertion timing after the assertion of nIRQ or nFIQ inputs.

Figure 2.12. STANDBYWFI deassertion timing

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Processor Wait for Event

Wait for Event is a feature of the ARMv7-A architecture that uses a locking mechanism based on events to put the processor in a low power state by disabling most of the clocks in the processor while keeping the processor powered up. This reduces the power drawn to the static leakage current, leaving a small clock power overhead to enable the processor to wake up from WFE mode.

A processor enters into WFE mode by executing the WFE instruction. When executing the WFE instruction, the processor waits for all instructions in the processor to complete before entering the idle or low power state. The WFE instruction ensures that all explicit memory accesses occurred before the WFE instruction in program order, have completed.

While the processor is in WFE mode, the clocks in the processor are temporarily enabled without causing the processor to exit WFE mode, when any of the following events are detected:

  • an L2 snoop request that must be serviced by the processor L1 data cache

  • a cache, TLB or BTB maintenance operation that must be serviced by the processor L1 instruction cache, data cache, instruction TLB, data TLB, or BTB

  • an APB access to the debug or trace registers residing in the processor power domain.

Exit from WFE mode occurs when the processor detects a reset, the assertion of the EVENTI input signal, or one of the WFI wake up events as described in the ARM Architecture Reference Manual.

On entry into WFE mode, STANDBYWFE for that processor is asserted. Assertion of STANDBYWFE guarantees that the processor is in idle and low power state. STANDBYWFE continues to assert even if the clocks in the processor are temporarily enabled because of an L2 snoop request, cache, TLB, and BTB maintenance operation or an APB access.

The upper bound for the STANDBYWFE deassertion timing after the assertion of nIRQ or nFIQ inputs is identical to STANDBYWFI as shown in Figure 2.12.

L2 Wait for Interrupt

When all the processors are in WFI mode, the shared L2 memory system logic that is common to all the processors can also enter a WFI mode. In L2 WFI mode, all internal clocks in the processor are disabled, with the exception of the asynchronous Debug PCLKDBG domain.

Entry into L2 WFI mode can only occur if specific requirements are met and the following sequence applied:

  • All processors are in WFI mode and therefore, all the processors STANDBYWFI outputs are asserted. Assertion of all the processors STANDBYWFI outputs guarantee that all the processors are in idle and low power state. All clocks in the processor, with the exception of a small amount of clock wake up logic, are disabled.

  • The SoC asserts the input pin ACINACTM after all responses are received and before it sends any new transactions on the AXI master interface. This prevents the L2 memory system from accepting any new requests from the AXI master interface and ensures that all outstanding transactions are complete.

  • The SoC asserts the input pin AINACTS after all responses are received and before it sends any new transactions on the ACP slave interface. This prevents the L2 memory system from accepting any new requests from the ACP slave interface and ensures that all outstanding transactions are complete.

  • When the L2 memory system completed the outstanding transactions for AXI interfaces, it can then enter the low power state, L2 WFI mode. On entry into L2 WFI mode, STANDBYWFIL2 is asserted. Assertion of STANDBYWFIL2 guarantees that the L2 is in idle and does not accept any new transactions.

  • The SoC can then deassert the CLKEN input to the Cortex-A15 processor to stop all remaining internal clocks within the Cortex-A15 processor that are derived from CLK. All clocks in the shared L2 memory system logic, Interrupt Controller and Timer, with the exception of a small clock wake up logic, are disabled.

The SoC must assert the CLKEN input on a WFI wake up event to enable the L2 memory system and the processor to wake up from WFI mode. Exit from L2 WFI mode occurs on one of the following WFI wake up events:

  • a physical IRQ or FIQ interrupt

  • a debug event

  • power-on or soft reset.

When the processor exits from WFI mode, STANDBYWFI for that processor is deasserted. When the L2 memory system logic exits from WFI mode, STANDBYWFIL2 is deasserted. The SoC must continue to assert ACINACTM and AINACTS until STANDBWFIL2 has deasserted.

Figure 2.13 shows the L2 WFI timing for a 4-processor configuration.

Figure 2.13. L2 Wait For Interrupt timing

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NEON and VFP clock gating

The Cortex-A15 processor supports dynamic high-level clock gating of the NEON and VFP unit to reduce dynamic power dissipation.

With the NEON and VFP unit powered up, the clock to the unit is enabled when an Advanced SIMD or VFP instruction is detected in the pipeline, and is disabled otherwise.

You can set bit [29] of the Auxiliary Control Register, ACTLR, to 1 to disable dynamic clock gating of the NEON and VFP unit. See Auxiliary Control Register.

L2 control and tag banks clock gating

The Cortex-A15 processor supports dynamic high-level clock gating of the shared L2 control logic and the four L2 tag banks to reduce dynamic power dissipation.

The L2 tag bank clocks are only enabled when a corresponding access is detected in the pipeline.

The L2 control logic is disabled after 256 consecutive idle cycles. It is then enabled when an L2 access is detected, with an additional 4-cycle penalty for the wake up before the access is serviced.

You can set bit [28] of the L2 Auxiliary Control Register, L2ACTLR, to 1 to disable dynamic clock gating of the L2 tag banks. See L2 Auxiliary Control Register.

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